Lines Matching +full:tri +full:- +full:default

1 //===- InterferenceCache.h - Caching per-block interference ----*- C++ -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // InterferenceCache remembers per-block interference from LiveIntervalUnions,
12 //===----------------------------------------------------------------------===//
33   /// BlockInterference - information about the interference in a single basic
40     BlockInterference() = default;
43   /// Entry - A cache entry containing interference information for all aliases
46     /// PhysReg - The register currently represented.
49     /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
53     /// RefCount - The total number of Cursor instances referring to this Entry.
56     /// MF - The current function.
59     /// Indexes - Mapping block numbers to SlotIndex ranges.
62     /// LIS - Used for accessing register mask interference maps.
65     /// PrevPos - The previous position the iterators were moved to.
68     /// RegUnitInfo - Information tracked about each RegUnit in PhysReg.
94     /// Blocks - Interference for each block in the function.
97     /// update - Recompute Blocks[MBBNum]
101     Entry() = default;
117     void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
119     /// valid - Return true if this is a valid entry for physReg.
120     bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
122     /// reset - Initialize entry to represent physReg's aliases.
124                const TargetRegisterInfo *TRI, const MachineFunction *MF);
126     /// get - Return an up to date BlockInterference.
135   // much memory. Instead, a fixed number of cache entries are used in a round-
139   const TargetRegisterInfo *TRI = nullptr;  variable
148   // Next round-robin entry to be picked.
154   // get - Get a valid entry for PhysReg.
158   InterferenceCache() = default;
167   /// init - Prepare cache for a new function.
170             const TargetRegisterInfo *tri);
172   /// getMaxCursors - Return the maximum number of concurrent cursors that can
176   /// Cursor - The primary query interface for the block interference cache.
187         CacheEntry->addRef(-1);  in setEntry()
190         CacheEntry->addRef(+1);  in setEntry()
194     /// Cursor - Create a dangling cursor.
195     Cursor() = default;
208     /// setPhysReg - Point this cursor to PhysReg's interference.
217     /// moveTo - Move cursor to basic block MBBNum.
219       Current = CacheEntry ? CacheEntry->get(MBBNum) : &NoInterference;  in moveToBlock()
222     /// hasInterference - Return true if the current block has any interference.
224       return Current->First.isValid();  in hasInterference()
227     /// first - Return the starting index of the first interfering range in the
230       return Current->First;  in first()
233     /// last - Return the ending index of the last interfering range in the
236       return Current->Last;  in last()