1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
23 #include "llvm/Config/llvm-config.h"
51 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
53 //------------------------------------------------------------------------------
55 //------------------------------------------------------------------------------
64     assert(RegBanks[Idx]->getID() == Idx &&  in RegisterBankInfo()
70 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {  in verify()
77     assert(RegBank.verify(*this, TRI) && "RegBank is invalid");  in verify()
85                              const TargetRegisterInfo &TRI) const {  in getRegBank()
89     const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg, TRI);  in getRegBank()
104                                          const TargetRegisterInfo &TRI) const {  in getMinimalPhysRegClass()
108     return RegRCIt->second;  in getMinimalPhysRegClass()
109   const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClassLLT(Reg, LLT());  in getMinimalPhysRegClass()
117   const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();  in getRegBankFromConstraints()  local
121   const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI);  in getRegBankFromConstraints()
144   if (RB && !RB->covers(RC))  in constrainGenericRegister()
175   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();  in getInstrMappingImpl()  local
195     // is the best default mapping for the current instruction.  Keep  in getInstrMappingImpl()
198     const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);  in getInstrMappingImpl()
199     // For copy-like instruction, we want to reuse the register bank  in getInstrMappingImpl()
218     unsigned Size = getSizeInBits(Reg, MRI, TRI);  in getInstrMappingImpl()
225                                               MRI, TRI);  in getInstrMappingImpl()
232       // The default handling assumes any register bank can be copied to any  in getInstrMappingImpl()
243         const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);  in getInstrMappingImpl()
245             cannotCopy(*CurRegBank, *AltRegBank, getSizeInBits(Reg, MRI, TRI)))  in getInstrMappingImpl()
271   return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);  in hashPartialMapping()
289     return *It->second;  in getPartialMapping()
323     return *It->second;  in getValueMapping()
397     return *It->second;  in getInstructionMappingImpl()
420     // Put the default mapping first.  in getInstrPossibleMappings()
429     assert(Mapping->verify(MI) && "Mapping is invalid");  in getInstrPossibleMappings()
443   LLVM_DEBUG(dbgs() << "Applying default-like mapping\n");  in applyDefaultMapping()
483       // The default mapping is not supposed to change the size of  in applyDefaultMapping()
489           "Types with difference size cannot be handled by the default "  in applyDefaultMapping()
501                                          const TargetRegisterInfo &TRI) const {  in getSizeInBits()
507     auto *RC = getMinimalPhysRegClass(Reg, TRI);  in getSizeInBits()
509     return TRI.getRegSizeInBits(*RC);  in getSizeInBits()
511   return TRI.getRegSizeInBits(Reg, MRI);  in getSizeInBits()
514 //------------------------------------------------------------------------------
516 //------------------------------------------------------------------------------
530   assert(RBI.getMaximumSize(RegBank->getID()) >= Length &&  in verify()
549     if (Part->Length != First->Length || Part->RegBank != First->RegBank)  in partsAllUniform()
623              "We should not care about non-reg mapping");  in verify()
638     assert(MOMapping.verify(*RBI, RBI->getSizeInBits(  in verify()
664 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
677   assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");  in getVRegsMem()
700   return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);  in getNewVRegsEnd()
713   assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");  in createVRegs()
719     assert(PartMap != ValMapping.end() && "Out-of-bound access");  in createVRegs()
726     NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));  in createVRegs()
727     MRI.setRegBank(NewVReg, *PartMap->RegBank);  in createVRegs()
735   assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");  in setVRegs()
738          "Out-of-bound access for partial mapping");  in setVRegs()
750   assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");  in getVRegs()
799   const TargetRegisterInfo *TRI =  in print()  local
801           ? getMI().getMF()->getSubtarget().getRegisterInfo()  in print()
810     OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";  in print()
816       OS << printReg(VReg, TRI);  in print()