Lines Matching +full:tri +full:- +full:default
1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
34 const SITargetLowering *TLI = STI->getTargetLowering(); in getTM()
35 return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine()); in getTM()
90 // Non-entry functions have no special inputs for now, other registers in SIMachineFunctionInfo()
98 if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr")) in SIMachineFunctionInfo()
114 if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x")) in SIMachineFunctionInfo()
117 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y")) in SIMachineFunctionInfo()
120 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z")) in SIMachineFunctionInfo()
125 if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x")) in SIMachineFunctionInfo()
128 if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") && in SIMachineFunctionInfo()
132 if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") && in SIMachineFunctionInfo()
136 if (!IsKernel && !F.hasFnAttribute("amdgpu-no-lds-kernel-id")) in SIMachineFunctionInfo()
157 Attribute A = F.getFnAttribute("amdgpu-git-ptr-high"); in SIMachineFunctionInfo()
162 A = F.getFnAttribute("amdgpu-32bit-address-high-bits"); in SIMachineFunctionInfo()
172 AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1); in SIMachineFunctionInfo()
191 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer() argument
193 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
199 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr() argument
200 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
206 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr() argument
207 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
213 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr() argument
215 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
221 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) { in addDispatchID() argument
222 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
228 Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit() argument
229 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
235 Register SIMachineFunctionInfo::addPrivateSegmentSize(const SIRegisterInfo &TRI) { in addPrivateSegmentSize() argument
241 Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) { in addImplicitBufferPtr() argument
242 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
255 const SIRegisterInfo &TRI, const TargetRegisterClass *RC, in addPreloadedKernArg() argument
264 TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC); in addPreloadedKernArg()
299 // Separate out the callee-saved and scratch registers.
325 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in shiftSpillPhysVGPRsToLowestRange() local
329 TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF); in shiftSpillPhysVGPRsToLowestRange()
368 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocatePhysicalVGPRForSGPRSpills() local
375 LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF, in allocatePhysicalVGPRForSGPRSpills()
421 assert(ST.getRegisterInfo()->spillSGPRToVGPR() && in allocateSGPRSpillToVGPRLane()
435 NumSpillLanes -= I; in allocateSGPRSpillToVGPRLane()
470 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in allocateVGPRSpillToAGPR() local
476 OtherUsedRegs.resize(TRI->getNumRegs()); in allocateVGPRSpillToAGPR()
479 TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv()); in allocateVGPRSpillToAGPR()
491 for (int I = NumLanes - 1; I >= 0; --I) { in allocateVGPRSpillToAGPR()
505 MRI.reserveReg(*NextSpillReg, TRI); in allocateVGPRSpillToAGPR()
518 // any re-mapping of freed frame indices by later pass(es) like "stack slot in removeDeadFrameIndices()
536 // All other SGPRs must be allocated on the default stack, so reset the in removeDeadFrameIndices()
542 MFI.setStackID(I, TargetStackID::Default); in removeDeadFrameIndices()
558 const SIRegisterInfo &TRI) { in getScavengeFI() argument
563 MFI.CreateStackObject(TRI.getSpillSize(AMDGPU::SGPR_32RegClass), in getScavengeFI()
564 TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false); in getScavengeFI()
601 default: in getGITPtrLoReg()
609 const TargetRegisterInfo &TRI) { in regToString() argument
613 OS << printReg(Reg, &TRI); in regToString()
620 const TargetRegisterInfo &TRI) { in convertArgumentInfo() argument
632 OS << printReg(Arg.getRegister(), &TRI); in convertArgumentInfo()
672 const llvm::SIMachineFunctionInfo &MFI, const TargetRegisterInfo &TRI, in SIMachineFunctionInfo() argument
684 ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)), in SIMachineFunctionInfo()
685 FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)), in SIMachineFunctionInfo()
686 StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)), in SIMachineFunctionInfo()
689 ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), in SIMachineFunctionInfo()
694 WWMReservedRegs.push_back(regToString(Reg, TRI)); in SIMachineFunctionInfo()
697 LongBranchReservedReg = regToString(MFI.getLongBranchReservedReg(), TRI); in SIMachineFunctionInfo()
699 VGPRForAGPRCopy = regToString(MFI.getVGPRForAGPRCopy(), TRI); in SIMachineFunctionInfo()
702 SGPRForEXECCopy = regToString(MFI.getSGPRForEXECCopy(), TRI); in SIMachineFunctionInfo()
735 auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo()); in initializeBaseYamlFields()
739 *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID()); in initializeBaseYamlFields()
744 SourceRange = YamlMFI.ScavengeFI->SourceRange; in initializeBaseYamlFields()
755 return !F.hasFnAttribute("amdgpu-no-agpr"); in mayUseAGPRs()