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/freebsd/sys/contrib/device-tree/Bindings/soc/microchip/
H A Datmel,at91rm9200-tcb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Timer Counter Block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
14 timer has three channels with two counters each.
19 - enum:
20 - atmel,at91rm9200-tcb
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This hardware block provides 3 types of timer along with PWM functionality:
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
12 by a programmable prescaler, break input feature, PWM outputs and
13 complementary PWM outputs channels.
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15 driven by a programmable prescaler and PWM outputs.
[all …]
H A Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
[all …]
H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dpwm-omap-dmtimer.txt1 * OMAP PWM for dual-mode timers
4 - compatible: Shall contain "ti,omap-dmtimer-pwm".
5 - ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info
7 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
11 - ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
12 - ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
13 - 0x00 - high-frequency system clock (timer_sys_ck)
14 - 0x01 - 32-kHz always-on clock (timer_32k_ck)
15 - 0x02 - external clock (timer_ext_ck, OMAP2 only)
18 pwm9: dmtimer-pwm@9 {
[all …]
H A Dsnps,dw-apb-timers-pwm2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Synopsys DW-APB timers PWM controller
11 - Ben Dooks <ben.dooks@sifive.com>
14 This describes the DesignWare APB timers module when used in the PWM
24 - $ref: pwm.yaml#
28 const: snps,dw-apb-timers-pwm2
33 "#pwm-cells":
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesa
[all...]
H A Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ingeni
[all...]
H A Dcdns,ttc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence TTC - Triple Timer Counter
10 - Michal Simek <michal.simek@amd.com>
22 A list of 3 interrupts; one per timer channel.
27 power-domains:
30 timer-width:
33 Bit width of the timer, necessary if not 16.
[all …]
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
H A Dandestech,atcpit100-timer.txt1 Andestech ATCPIT100 timer
2 ------------------------------------------------------------------
6 This timer is a set of compact multi-function timers, which can be
7 used as pulse width modulators (PWM) as well as simple timers.
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
[all …]
H A Dxlnx,xps-timer.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
20 clock-names:
29 '#pwm-cells': true
31 xlnx,count-width:
[all …]
H A Dti,timer.txt1 OMAP Timer bindings
4 - compatible: Should be set to one of the below. Please note that
5 OMAP44xx devices have timer instances that are 100%
8 So for OMAP44xx devices timer instances may use
11 ti,omap2420-timer (applicable to OMAP24xx devices)
12 ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
13 ti,omap4430-timer (applicable to OMAP44xx devices)
14 ti,omap5430-timer (applicable to OMAP543x devices)
15 ti,am335x-timer (applicable to AM335x devices)
16 ti,am335x-timer-1ms (applicable to AM335x devices)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91-kizbox.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board
5 * Copyright (C) 2012-2014 Boris BREZILLON <b.brezillon@overkiz.com>
6 * 2014-2015 Gaël PORTAY <g.portay@overkiz.com>
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
18 stdout-path = &dbgu;
27 clock-frequency = <18432000>;
31 gpio-keys {
32 compatible = "gpio-keys";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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H A Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 * The MCU domain timer interrupts are routed only to the ESM module,
14 mcu_timer0: timer@4800000 {
15 compatible = "ti,am654-timer";
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
24 mcu_timer1: timer@4810000 {
25 compatible = "ti,am654-timer";
[all …]
H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
[all …]
H A Dk3-am62a-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
19 compatible = "ti,j721e-esm";
21 bootph-pre-ram;
23 ti,esm-pins = <0>, <1>, <2>, <85>;
27 * The MCU domain timer interrupts are routed only to the ESM module,
[all …]
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa25x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "dt-bindings/clock/pxa-clock.h"
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "marvell,pxa250-core-clocks";
23 #clock-cells = <1>;
27 /* timer oscillator */
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <3686400>;
[all …]

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