Lines Matching +full:timer +full:- +full:pwm

1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
10 	 * The MCU domain timer interrupts are routed only to the ESM module,
14 	mcu_timer0: timer@4800000 {
15 		compatible = "ti,am654-timer";
18 		clock-names = "fck";
19 		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 		ti,timer-pwm;
24 	mcu_timer1: timer@4810000 {
25 		compatible = "ti,am654-timer";
28 		clock-names = "fck";
29 		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
30 		ti,timer-pwm;
34 	mcu_timer2: timer@4820000 {
35 		compatible = "ti,am654-timer";
38 		clock-names = "fck";
39 		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
40 		ti,timer-pwm;
44 	mcu_timer3: timer@4830000 {
45 		compatible = "ti,am654-timer";
48 		clock-names = "fck";
49 		power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
50 		ti,timer-pwm;
55 		compatible = "ti,am64-uart", "ti,am654-uart";
58 		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
60 		clock-names = "fclk";
65 		compatible = "ti,am64-uart", "ti,am654-uart";
68 		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
70 		clock-names = "fclk";
75 		compatible = "ti,am64-i2c", "ti,omap4-i2c";
78 		#address-cells = <1>;
79 		#size-cells = <0>;
80 		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
82 		clock-names = "fck";
87 		compatible = "ti,am64-i2c", "ti,omap4-i2c";
90 		#address-cells = <1>;
91 		#size-cells = <0>;
92 		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
94 		clock-names = "fck";
99 		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
102 		#address-cells = <1>;
103 		#size-cells = <0>;
104 		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
110 		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
113 		#address-cells = <1>;
114 		#size-cells = <0>;
115 		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
120 	mcu_gpio_intr: interrupt-controller@4210000 {
121 		compatible = "ti,sci-intr";
123 		ti,intr-trigger-type = <1>;
124 		interrupt-controller;
125 		interrupt-parent = <&gic500>;
126 		#interrupt-cells = <1>;
128 		ti,sci-dev-id = <5>;
129 		ti,interrupt-ranges = <0 104 4>;
133 		compatible = "ti,am64-gpio", "ti,keystone-gpio";
135 		gpio-controller;
136 		#gpio-cells = <2>;
137 		interrupt-parent = <&mcu_gpio_intr>;
139 		interrupt-controller;
140 		#interrupt-cells = <2>;
142 		ti,davinci-gpio-unbanked = <0>;
143 		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
145 		clock-names = "gpio";
149 		bootph-all;
150 		compatible = "pinctrl-single";
152 		#pinctrl-cells = <1>;
153 		pinctrl-single,register-width = <32>;
154 		pinctrl-single,function-mask = <0xffffffff>;
158 		bootph-pre-ram;
159 		compatible = "ti,j721e-esm";
161 		ti,esm-pins = <0>, <1>;