| /freebsd/contrib/ntp/ntpd/ |
| H A D | ntp_loopfilter.c | 2 * ntp_loopfilter.c - implements the NTP loop filter algorithm
33 * in UDel TR 97-4-3, as amended. It operates as an adaptive parameter,
34 * hybrid phase/frequency-lock loop. A number of sanity checks are
41 #define CLOCK_PHI 15e-6 /* max frequency error (s/s) */
47 #define CLOCK_LIMIT 30 /* poll-adjust threshold */
48 #define CLOCK_PGATE 4. /* poll-adjust gate */
60 * NSET FREQ step, FREQ freq no
1072 set_freq(double freq) set_freq() argument
1243 loop_config(int item,double freq) loop_config() argument
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| H A D | refclock_wwv.c | 2 * refclock_wwv - clock driver for NIST WWV/H time/frequency station
43 * kHz and mu-law companding. This is the same standard as used by the
53 * Report 97-8-1, University of Delaware, August 1997, 25 pp., available
61 * a nonzero ICOM ID select code. The C-IV trace is turned on if the
68 * port, where 0 is the mike port (default) and 1 is the line-in port.
74 * CEVNT_PROP propagation failure - no stations heard
82 #define PRECISION (-10) /* precision assumed (about 1 ms) */
99 #define AUDIO_PHI 5e-6 /* dispersion growth factor */
120 * on signal loss. SSYNC is set when the second sync puls
480 struct sync { global() struct
482 maxengsync global() argument
483 noiengsync global() argument
486 mepochsync global() argument
488 ampsync global() argument
489 synengsync global() argument
490 synmaxsync global() argument
491 synsnrsync global() argument
504 refidsync global() argument
514 double phase, freq; /* logical clock phase and frequency */ global() member
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| H A D | refclock_irig.c | 2 * refclock_irig - audio IRIG-B/E demodulator/decoder
26 * Audio IRIG-B/E demodulator/decoder
29 * IRIG-B/E signals commonly produced by GPS receivers and other timing
30 * devices. The IRIG signal is an amplitude-modulated carrier with
31 * pulse-width modulated data bits. For IRIG-B, the carrier frequency is
32 * 1000 Hz and bit rate 100 b/s; for IRIG-E, the carrier frequenchy is
37 * kHz and mu-law companding. This is the same standard as used by the
43 * The program processes 8000-H
216 double phase, freq; /* logical clock phase and frequency */ global() member
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| H A D | ntp_util.c | 2 * ntp_util.c - stuff I didn't have any other place for
64 double wander_threshold = 1e-7; /* initial frequency threshold */
114 * uninit_util - free memory allocated by init_util
154 * init_util - initialize the util module of ntpd
179 * hourly_stats - print some interesting stats
199 * soft clock is kept in sync with the battery clock. If it in write_stats()
207 * battery clock sync up to system time. The way to do THAT is in write_stats()
219 * (prr) getpriority returns -1 on error, but -1 is also a valid in write_stats()
221 * call and check it for non-zer in write_stats()
625 record_loop_stats(double offset,double freq,double jitter,double wander,int spoll) record_loop_stats() argument
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| /freebsd/sys/dev/videomode/ |
| H A D | vesagtf.c | 3 /*-
43 * This has required the use of 64-bit integers in a few places, but
89 * Copyright (c) 1994, 1995, 1996 - Video Electronics Standards
120 * surrounding the addressable video); on most non-overscan type
172 * #define C_PRIME (((C - J) * K/256.0) + J)
180 #define C_PRIME256(p) (((p->C - p->J) * p->K) + (p->J * 256))
181 #define M_PRIME256(p) (p->K * p->M)
186 * print_value() - print the result of the named computation; this is
195 printf("%2d: %-27s: %u\n", n, name, val); in print_value()
202 * vert_refresh() - as defined by the GTF Timing Standard, compute the
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | max8952.txt | 4 - compatible: must be equal to "maxim,max8952"
5 - reg: I2C slave address, usually 0x60
6 - max8952,dvs-mode-microvolt: array of 4 integer values defining DVS voltages
8 - any required generic properties defined in regulator.txt
11 - max8952,vid-gpios: array of two GPIO pins used for DVS voltage selection
12 - max8952,en-gpio: GPIO used to control enable status of regulator
13 - max8952,default-mode: index of default DVS voltage, from <0, 3> range
14 - max8952,sync-freq: sync frequency, must be one of following values:
15 - 0: 26 MHz
16 - 1: 13 MHz
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| H A D | maxim,max8952.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
19 max8952,default-mode:
25 max8952,dvs-mode-microvolt:
35 max8952,en-gpio:
40 max8952,ramp-speed:
46 - 0: 32mV/us
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| /freebsd/sys/powerpc/mpc85xx/ |
| H A D | platform_mpc85xx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2008-2012 Semihalf.
154 if ((cpus = OF_finddevice("/cpus")) != -1) { in mpc85xx_attach()
167 ccsr = -1; in mpc85xx_attach()
168 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++) in mpc85xx_attach()
170 if (ccsr == -1) { in mpc85xx_attach()
187 if (ccsr == -1) in mpc85xx_attach()
190 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells)); in mpc85xx_attach()
191 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells)); in mpc85xx_attach()
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| H A D | mpc85xx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
169 (flsl(size + (size - 1)) - 2))
235 trgt = -1; in law_pci_target()
287 /* Read back to sync write */ in l3cache_enable()
333 static uint32_t freq; in mpc85xx_get_platform_clock() local
335 if (freq != 0) in mpc85xx_get_platform_clock()
336 return (freq); in mpc85xx_get_platform_clock()
340 /* freq isn't modified on error. */ in mpc85xx_get_platform_clock()
341 OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq)); in mpc85xx_get_platform_clock()
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| H A D | fsl_diu.c | 1 /*-
84 #define DIU_HSYN_PARA 0x034 /* Horizontal Sync Parameter */
88 #define DIU_VSYN_PARA 0x038 /* Vertical Sync Parameter */
121 #define DIU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1)
179 { -1, 0 }
205 reg = bus_read_4(sc->res[0], DIU_INT_STATUS); in diu_intr()
206 bus_write_4(sc->res[0], DIU_INT_STATUS, reg); in diu_intr()
212 diu_set_pxclk(device_t dev, unsigned int freq) in diu_set_pxclk() argument
223 /* freq is in kHz */ in diu_set_pxclk()
224 freq *= 1000; in diu_set_pxclk()
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| /freebsd/contrib/ntp/html/ |
| H A D | clock.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
12 <!-- #BeginDate format:En2m -->4-Aug-2011 23:40<!-- #EndDate -->
28 …-of-year (TOY) chip to maintain the time when the power is off. When the computer is restarted, t…
31 …emon sets the step threshold to 600 s using the <tt>-x</tt> option on the command line. If the <tt…
33 …idered before using these options. The slew rate is fixed at 500 parts-per-million (PPM) by th…
45 <dt>Sync Interval</dt>
51 <dt>FSET - The frequency file is present</dt>
52 <dd> Load the frequency file, initialize the hold timer and continue in SYNC state.</dd>
53 <dt>NSET - The frequency file is not present</dt>
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| /freebsd/sys/x86/x86/ |
| H A D | delay.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
57 * on different CPUs are not in sync. in delay_tsc()
74 uint64_t end, freq, now; in delay_tc() local
78 * Only use the TSC if it is P-state invariant. If the TSC is in delay_tc()
79 * not P-state invariant and the CPU is not running at the in delay_tc()
80 * "full" P-state, then the TSC will increment at some rate in delay_tc()
88 if (tc->tc_quality <= 0) in delay_tc()
90 func = tc->tc_get_timecount; in delay_tc()
91 mask = tc->tc_counter_mask; in delay_tc()
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| /freebsd/lib/libsys/ |
| H A D | ntp_adjtime.2 | 61 to adjust the phase and frequency of the phase- or frequency-lock loop
66 function provides the time, maximum error (sync distance) and
78 .Bd -literal
82 long freq; /* frequency offset (scaled ppm) (rw) */
91 * The following read-only structure members are implemented
109 .Bl -tag -width tolerance -compact
113 call (write-only).
115 .Bl -tag -width MOD_TIMECONST -compact -offset indent
135 system time in small increments (read-write).
136 .It Fa freq
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| /freebsd/contrib/ntp/include/ |
| H A D | mbg_gps166.h | 2 …* /src/NTP/REPOSITORY/ntp4-dev/include/mbg_gps166.h,v 4.7 2006/06/22 18:41:43 kardel RELEASE_20060…
11 * Copyright (c) 1997-2005 by Frank Kardel <kardel <AT> ntp.org>
77 * The Unix time_t epoch is usually 1970-01-01 00:00 whereas
78 * the GPS epoch is 1980-01-06 00:00, so the difference is 10 years,
80 * of the day-of-month (6 - 1), so:<br>
199 * The individual command codes are marked with (rwa) accordingly, where '-' is used
217 GPS_AUTO_ON = 0x000, ///< (-w-) no data, enable auto-msgs from device
218 GPS_AUTO_OFF, ///< (-w-) no data, disable auto-msgs from device
219 …GPS_SW_REV, ///< (r--) deprecated, ::SW_REV, software revision, use only if ::GPS_RECEIV…
220 …GPS_BVAR_STAT, ///< (r--) ::BVAR_STAT, status of buffered variables, only if ::GPS_MODEL_HA…
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| /freebsd/contrib/ntp/util/ |
| H A D | tg.c | 6 * broadcast timecode. Alternatively, it can generate the IRIG-B
24 * over the range 0-255. The signal generator by default uses WWV
26 * switches to IRIG-B format.
42 * the transmissionorder is low-order first as the frame is processed
44 * For IRIG the on-time marker M preceeds the first (units) bit, so its
64 #define SECOND 8000 /* one second of 125-us samples */
68 #define IRIG 1 /* IRIG-B encoder */
82 int c3000[] = {1, 48, 63, 70, 78, 82, 85, 89, 92, 94, /* 0-9 */
83 96, 98, 99, 100, 101, 101, 102, 103, 103, 103, /* 10-19 */
84 103, 103, 103, 103, 102, 101, 101, 100, 99, 98, /* 20-29 */
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|
| H A D | tg2.c | 6 * broadcast timecode. Alternatively, it can generate the IRIG-B
24 * over the range 0-255. The signal generator by default uses WWV
26 * switches to IRIG-B format.
42 * the transmissionorder is low-order first as the frame is processed
44 * For IRIG the on-time marker M preceeds the first (units) bit, so its
54 * v0.23 2007-02-12 dmw:
55 * - Changed statistics to include calculated error
60 * v0.22 2007-02-08 dmw:
61 * - Changed default for rate correction to "enabled", "-j" switch now disables.
62 * - Adjusted help message accordingly.
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| /freebsd/contrib/wpa/src/common/ |
| H A D | hw_features_common.c | 3 * Copyright (c) 2002-2013, Jouni Malinen <j@w1.fi>
20 int chan, int *freq) in hw_get_channel_chan() argument
24 if (freq) in hw_get_channel_chan()
25 *freq = 0; in hw_get_channel_chan()
30 for (i = 0; i < mode->num_channels; i++) { in hw_get_channel_chan()
31 struct hostapd_channel_data *ch = &mode->channels[i]; in hw_get_channel_chan()
32 if (ch->chan == chan) { in hw_get_channel_chan()
33 if (freq) in hw_get_channel_chan()
34 *freq = ch->freq; in hw_get_channel_chan()
44 hw_mode_get_channel(struct hostapd_hw_modes *mode, int freq, int *chan) in hw_mode_get_channel() argument
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| /freebsd/sys/dev/igc/ |
| H A D | igc_defines.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3399-gru-chromebook.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-o
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| /freebsd/contrib/opencsd/decoder/source/ |
| H A D | trc_gen_elem.cpp | 43 …{"OCSD_GEN_TRC_ELEM_UNKNOWN","Unknown trace element - default value or indicate error in stream to…
44 …{"OCSD_GEN_TRC_ELEM_NO_SYNC","Waiting for sync - either at start of decode, or after overflow / ba…
45 …{"OCSD_GEN_TRC_ELEM_TRACE_ON","Start of trace - beginning of elements or restart after discontinui…
54 {"OCSD_GEN_TRC_ELEM_TIMESTAMP","Timestamp - preceding elements happeded before this time."},
55 …{"OCSD_GEN_TRC_ELEM_CYCLE_COUNT","Cycle count - cycles since last cycle count value - associated w…
56 {"OCSD_GEN_TRC_ELEM_EVENT","Event - numbered event or trigger"},
57 …{"OCSD_GEN_TRC_ELEM_SWTRACE","Software trace packet - may contain data payload. STM / ITM hardware…
58 …{"OCSD_GEN_TRC_ELEM_SYNC_MARKER","Synchronisation marker - marks position in stream of an element …
60 …{"OCSD_GEN_TRC_ELEM_INSTRUMENTATION", "PE instrumentation trace - PE generated SW trace, applicati…
65 "--- ",
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| /freebsd/contrib/wpa/src/ap/ |
| H A D | ieee802_11.c | 3 * Copyright (c) 2002-2017, Jouni Malinen <j@w1.fi>
95 if (!hapd->conf->multi_ap) in hostapd_eid_multi_ap()
98 if (hapd->conf->multi_ap & BACKHAUL_BSS) in hostapd_eid_multi_ap()
100 if (hapd->conf->multi_ap & FRONTHAUL_BSS) in hostapd_eid_multi_ap()
103 if (hapd->conf->multi_ap_client_disallow & in hostapd_eid_multi_ap()
107 if (hapd->conf->multi_ap_client_disallow & in hostapd_eid_multi_ap()
112 multi_ap.profile = hapd->conf->multi_ap_profile; in hostapd_eid_multi_ap()
113 multi_ap.vlanid = hapd->conf->multi_ap_vlanid; in hostapd_eid_multi_ap()
125 if (hapd->iface->current_rates == NULL) in hostapd_eid_supp_rates()
129 num = hapd->iface->num_rates; in hostapd_eid_supp_rates()
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| /freebsd/sys/arm/ti/am335x/ |
| H A D | am335x_lcd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
176 #define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
177 #define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
178 #define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
179 device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF)
180 #define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx);
182 #define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg);
184 bus_write_4((_sc)->sc_mem_res, reg, value);
190 #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end)
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| /freebsd/sys/arm/nvidia/drm2/ |
| H A D | tegra_hdmi.c | 1 /*-
58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v))
59 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, 4 * (_r))
205 {"nvidia,tegra124-hdmi", 1},
225 return -EINVAL; in drm_hdmi_avi_infoframe_from_display_mode()
231 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in drm_hdmi_avi_infoframe_from_display_mode()
232 frame->pixel_repeat = 1; in drm_hdmi_avi_infoframe_from_display_mode()
234 frame->video_code = drm_match_cea_mode(mode); in drm_hdmi_avi_infoframe_from_display_mode()
236 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; in drm_hdmi_avi_infoframe_from_display_mode()
242 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || in drm_hdmi_avi_infoframe_from_display_mode()
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| /freebsd/sys/dev/ath/ath_hal/ |
| H A D | ah_eeprom_v3.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
31 #define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */
33 #define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE)
37 #define AR_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */
38 #define AR_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */
43 #define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE)
78 /* XXX used to index various EEPROM-derived data structures */
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| /freebsd/sys/dev/iicbus/rtc/ |
| H A D | nxprtc.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Driver for NXP real-time clock/calendar chips:
31 * - PCF8563 = low power, countdown timer
32 * - PCA8565 = like PCF8563, automotive temperature range
33 * - PCF8523 = low power, countdown timer, oscillator freq tuning, 2 timers
34 * - PCF2127 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, 512B ram
35 * - PCA2129 = like PCF8523, automotive, tcxo, tamper/ts, i2c & spi, (note 1)
36 * - PCF2129 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, (note 1)
41 * in sync when the STOP bit is cleared after the time and timer registers are
[all …]
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