| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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| H A D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
9 A hart context is a privilege mode in a hardware execution thread. For example,
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
11 privilege modes per hart; machine mode and supervisor mode.
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
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| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
17 A hart context is a privilege mode in a hardware execution thread. For example,
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /freebsd/sys/riscv/riscv/ |
| H A D | exception.S | 1 /*-
2 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
41 .macro save_registers mode argument
42 addi sp, sp, -(TF_SIZE)
48 .if \mode == 0 /* We came from userspace. */
89 .if \mode == 1
105 .if \mode == 1
106 /* Disable user address access for supervisor mode exceptions. */
116 .macro load_registers mode argument
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| H A D | swtch.S | 1 /*-
2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
44 * Enable FPE usage in supervisor mode,
86 /* Disable FPE usage in supervisor mode. */
93 * Enable FPE usage in supervisor mode,
135 /* Disable FPE usage in supervisor mode. */
157 * Enable FPE usage in supervisor mode,
197 /* Disable FPE usage in supervisor mode. */
224 /* s[0-11] */
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| H A D | identcpu.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
76 /* Supervisor-mode extension support. */
82 /* Z-extensions support. */
90 u_int isa_extensions; /* Single-letter extensions. */
98 u_int z_extensions; /* Multi-letter extensions. */
109 * Micro-architecture tables.
116 #define MARCHID_END { -1ul, NULL }
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFeatures.td | 1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // RISC-V subtarget features and instruction predicates.
11 //===----------------------------------------------------------------------===//
13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V
16 // name - Name of the extension in lower case.
17 // major - Major version of extension.
18 // minor - Minor version of extension.
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| H A D | RISCVSystemOperands.td | 1 //===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // RISC-V system instruction.
12 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
31 // Privilege Mode: User = 0, System = 1 or Machine = 3.
32 // bits<2> ReadWrite = op{11 - 10};
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| /freebsd/usr.sbin/daemon/ |
| H A D | daemon.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
84 enum daemon_mode mode; member
124 { "change-dir", no_argument, NULL, 'c' },
125 { "close-fds", no_argument, NULL, 'f' },
128 { "output-file", required_argument, NULL, 'o' },
129 { "output-mask", required_argument, NULL, 'm' },
130 { "child-pidfile", required_argument, NULL, 'p' },
131 { "supervisor-pidfile", required_argument, NULL, 'P' },
133 { "restart-count", required_argument, NULL, 'C' },
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| /freebsd/sys/powerpc/include/ |
| H A D | bat.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause AND BSD-4-Clause
32 /*-
77 #define BAT_W 0x00000040 /* 1 = write-through, 0 = write-back */
83 #define BAT_PP_RO_S 0x00000001 /* read-only (soft) */
85 #define BAT_PP_RO 0x00000003 /* read-only */
90 #define BAT_Vs 0x00000002 /* valid in supervisor mode */
91 #define BAT_Vu 0x00000001 /* valid in user mode */
122 #define BAT601_W 0x00000040 /* 1 = write-through, 0 = write-back */
125 #define BAT601_Ks 0x00000008 /* key-supervisor */
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| H A D | slb.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 * PowerPC Microprocessor Family: The Programming Environments for 64-bit
42 #define SLBV_KS 0x0000000000000800UL /* Supervisor-state prot key */
43 #define SLBV_KP 0x0000000000000400UL /* User-state prot key */
44 #define SLBV_N 0x0000000000000200UL /* No-execute protection */
57 * 0x13bbUL) & (KERNEL_VSID_BIT - 1)) | \
66 * SLB page sizes encoding, as present in property ibm,segment-page-sizes
73 /* Virtual real-mode VSID in LPARs */
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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| /freebsd/sys/amd64/amd64/ |
| H A D | fpu.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
149 * must be 64-byte aligned.
165 int use_xsave; /* non-static for cpu_switch.S */
321 * read-only before cpu_startup(). in fpuinit_bsp1()
423 XSAVE_AREA_ALIGN - 1, 0); in fpuinitstate()
437 if (fpu_initialstate->sv_env.en_mxcsr_mask) in fpuinitstate()
438 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; in fpuinitstate()
450 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); in fpuinitstate()
451 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); in fpuinitstate()
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| /freebsd/sys/riscv/include/ |
| H A D | md_var.h | 1 /*-
44 /* Supervisor-mode extension support */
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| /freebsd/share/man/man7/ |
| H A D | mitigations.7 | 1 .\"-
2 .\" SPDX-License-Identifer: BSD-2-Clause
42 Some of these mitigations have run-time controls to enable them on a global
43 or per-process basis, some are optionally enabled or disabled at compile time,
48 .Bl -bullet -compact
58 Relocation Read-Onl
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| /freebsd/sys/amd64/ia32/ |
| H A D | ia32_exception.S | 1 /*-
38 * that it originated in supervisor mode and skip the swapgs.
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| /freebsd/stand/i386/btx/btx/ |
| H A D | btx.S | 22 .set MEM_ESP0,0x1800 # Supervisor stack
24 .set MEM_ESPR,0x5e00 # Real mode stack
44 .set PSL_VM,0x00020000 # Virtual 8086 mode flag
49 .set SEL_SCODE,0x8 # Supervisor code
50 .set SEL_SDATA,0x10 # Supervisor data
51 .set SEL_RCODE,0x18 # Real mode code
52 .set SEL_RDATA,0x20 # Real mode data
92 .set SCR_MAT,0x7 # Mode/attribute
99 .set BDA_SCR,0x449 # Video mode
106 .set _TSSIO,MEM_MAP-MEM_TSS # TSS I/O base
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| /freebsd/sys/contrib/xen/ |
| H A D | features.h | 45 * If set, the guest does not need to write-protect its pagetables, and can
51 * If set, the guest does not need to write-protect its segment descriptor
57 * If set, translation between the guest's 'pseudo-physical' address space
59 * mode the guest does not need to perform phys-to/from-machine translations
64 /* If set, the guest is running in supervisor mode (e.g., x86 ring 0). */
110 * must be located in lower 1MB, as required by ACPI Specification for IA-PC
118 * A direct-mapped (or 1:1 mapped) domain is a domain for which its
119 * local pages have gfn == mfn. If a domain is direct-mapped,
124 * - not auto_translated domains (x86 only) are always direct-mapped
125 * - on x86, auto_translated domains are not direct-mapped
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| /freebsd/usr.sbin/bhyve/amd64/ |
| H A D | task_switch.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
93 static_assert(sizeof(struct tss32) == 104, "compile-time assertion failed");
125 if (usd->sd_gran) in usd_to_seg_desc()
129 seg_desc.access = usd->sd_type | usd->sd_dpl << 5 | usd->sd_p << 7; in usd_to_seg_desc()
130 seg_desc.access |= usd->sd_xx << 12; in usd_to_seg_desc()
131 seg_desc.access |= usd->sd_def32 << 14; in usd_to_seg_desc()
132 seg_desc.access |= usd->sd_gran << 15; in usd_to_seg_desc()
154 * Bit 2 from the selector is retained as-is in the error code. in sel_exception()
170 * and non-zero otherwise.
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| /freebsd/contrib/llvm-project/clang/lib/Headers/ |
| H A D | uintrintrin.h | 1 /*===------------------ uintrintrin.h - UINTR intrinsics -------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
33 /// 64-bit mode, and software is not executing inside an enclave; otherwise,
34 /// each causes an invalid-opcode exception. Causes a transactional abort if
54 /// 64-bit mode, and software is not executing inside an enclave; otherwise,
55 /// each causes an invalid-opcode exception. Causes a transactional abort if
74 /// if CR4.UINT = 1, the logical processor is in 64-bit mode, and software is
75 /// not executing inside an enclave; otherwise, it causes an invalid-opcode
100 /// CR4.UINT = IA32_UINT_TT[0] = 1, the logical processor is in 64-bit mode,
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| /freebsd/sys/x86/include/ |
| H A D | specialreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
38 #define CR0_PE 0x00000001 /* Protected mode Enable */
51 #define CR0_NW 0x20000000 /* Not Write-through */
62 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
63 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
74 #define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */
75 #define CR4_LA57 0x00001000 /* Enable 5-level paging */
77 (Intel-specific) */
82 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution
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| /freebsd/tools/test/stress2/misc/ |
| H A D | syzkaller63.sh | 3 # Fatal trap 12: page fault while in kernel mode
6 # fault code = supervisor read data, page not present
26 # --- trap 0xc, eip = 0xfa1a2c, esp = 0x27a41a80, ebp = 0x27a41a98 ---
31 # --- syscall (486, FreeBSD ELF32, cpuset_getid), eip = 0x2056317d, esp = 0xffbfe990, ebp = 0xffbfe…
36 # version: FreeBSD 14.0-CURRENT #0 main-n260354-34b867ca30479: Mon Jan 30 07:26:30 CET 2023
42 [ `uname -p` = "i386" ] || exit 0
47 // Reported-by: syzbot+331e8402e0f7347f0f2a@syzkaller.appspotmail.com
64 syscall(SYS_mmap, 0x10000000, 0x1000000, 7, 0x1012, -1, 0);
69 mycc -o /tmp/$prog -Wall -Wextra -O0 /tmp/$prog.c || exit 1
71 (cd /tmp; timeout -k 3s 2s ./$prog)
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| /freebsd/sys/contrib/xen/arch-x86/ |
| H A D | cpufeatureset.h | 2 * arch-x86/cpufeatureset.h
32 * Simply #include <public/arch-x86/cpufeatureset.h>
78 * first space in the comment immediately following the feature value. Note -
91 * Lower case => Can be opted-in to, but not available by default.
94 /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */
96 XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */
100 XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */
111 XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */
118 XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */
120 XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */
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