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/linux/Documentation/devicetree/bindings/iio/pressure/
H A Dhoneywell,hsc030pa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Honeywell TruStability HSC and SSC pressure sensor series
10 support for Honeywell TruStability HSC and SSC digital pressure sensor
17 The vendor calls them "HSC series" and "SSC series". All of them have an
18 identical programming model but differ in pressure range, unit and transfer
21 To support different models one needs to specify the pressure range as well
22 as the transfer function. Pressure range can either be provided via
23 pressure-triplet (directly extracted from the part number) or in case it's
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/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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H A Dphy-miphy28lp.txt8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
13 provides. Address range information including the usual
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
24 - reg : Address and length of the register set for the device.
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/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
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/linux/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 bool ssc; member
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
373 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
374 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
386 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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/linux/sound/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 This driver requires the Atmel SSC driver for sound sink, a
25 called snd-at73c213.
31 range 8000 50000
/linux/block/
H A Dopal_proto.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * SPC-4 section
218 /* Locking state for a locking range */
283 * Opal SSC Documentation
337 * bits 6-7: reserved
369 * bits 1-6: reserved
380 * Enterprise SSC Feature
388 * bits 1-6: reserved
389 * bit 0: range crossing
419 * bits 3-7: reserved
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/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf4 Contact: linux-acpi@vger.kernel.org
6 (RO) The charger type - Traditional, Hybrid or NVDC.
11 Contact: linux-acpi@vger.kernel.org
19 Contact: linux-acpi@vger.kernel.org
27 Contact: linux-acpi@vger.kernel.org
33 - 0x00 = DC
34 - 0x01 = AC
35 - 0x02 = USB
36 - 0x03 = Wireless Charger
43 Contact: linux-acpi@vger.kernel.org
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/linux/drivers/iio/pressure/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 tristate "ROHM BM1390GLV-Z pressure sensor driver"
26 Support for the ROHM BM1390 pressure sensor. The BM1390GLV-Z
45 will be called bmp280 and you will also get bmp280-i2c for I2C
46 and/or bmp280-spi for SPI support.
104 will be called hid-sensor-press.
118 tristate "Honeywell HSC/SSC TruStability pressure sensor series"
126 HSC and SSC pressure and temperature sensor series.
142 tristate "InvenSense ICP-101xx pressure and temperature sensor"
146 Say yes here to build support for InvenSense ICP-101xx barometric
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H A Dhsc030pa.c1 // SPDX-License-Identifier: GPL-2.0-only
7 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
36 * HSC_PRESSURE_TRIPLET_LEN - length for the string that defines the
37 * pressure range, measurement unit and type as per the part nomenclature.
38 * Consult honeywell,pressure-triplet in the bindings file for details.
51 * function A: 10% - 90% of 2^14
52 * function B: 5% - 95% of 2^14
53 * function C: 5% - 85% of 2^14
54 * function F: 4% - 94% of 2^14
140 * struct hsc_range_config - list of pressure ranges based on nomenclature
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/linux/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c1 // SPDX-License-Identifier: GPL-2.0-only
68 struct i2c_adapter *adap = client->adapter; in ps8622_set()
72 msg.addr = client->addr + page; in ps8622_set()
80 client->addr + page, reg, val, ret); in ps8622_set()
86 struct i2c_client *cl = ps8622->client; in ps8622_send_config()
137 /* [7:5] DCO_FTRNG=+-40% */ in ps8622_send_config()
147 /* Gitune=-37% */ in ps8622_send_config()
167 /* [7:6] Right-bar GPIO output strength is 8mA */ in ps8622_send_config()
179 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config()
184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
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/linux/Documentation/scsi/
H A DFlashPoint.rst1 .. SPDX-License-Identifier: GPL-2.0
17 FREMONT, CA, -- October 8, 1996 -- Mylex Corporation has expanded Linux
33 Linux is a freely-distributed implementation of UNIX for Intel x86, Sun
35 machines. It supports a wide range of software, including the X Window
37 http://www.linux.org and http://www.ssc.com/.
55 and system boards. Through its wide range of RAID controllers and its
71 510/796-6100
78 BusLogic FlashPoint LT/BT-948 Upgrade Program
82 BusLogic FlashPoint LW/BT-958 Upgrade Program
99 customers to make sure the BT-946C/956C MultiMaster cards would still be
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
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H A Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
274 /* This macro returns ndiv effective scaled to SDM range */
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
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H A Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1 // SPDX-License-Identifier: MIT
196 * the range value for them is (actual_value - 2).
308 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
309 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
313 * divided-down version of it.
318 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
319 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
321 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
322 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
323 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
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H A Dintel_dp_mst.c59 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_dp_mst_max_dpt_bpp()
61 &crtc_state->hw.adjusted_mode; in intel_dp_mst_max_dpt_bpp()
67 * DSC->DPT interface width: in intel_dp_mst_max_dpt_bpp()
68 * ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used) in intel_dp_mst_max_dpt_bpp()
75 * testing on MTL-P the in intel_dp_mst_max_dpt_bpp()
76 * - DELL U3224KBA display in intel_dp_mst_max_dpt_bpp()
77 * - Unigraf UCD-500 CTS test sink in intel_dp_mst_max_dpt_bpp()
79 * - 5120x2880/995.59Mhz in intel_dp_mst_max_dpt_bpp()
80 * - 6016x3384/1357.23Mhz in intel_dp_mst_max_dpt_bpp()
81 * - 6144x3456/1413.39Mhz in intel_dp_mst_max_dpt_bpp()
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/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
293 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
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/linux/drivers/clk/ti/
H A Ddpll3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
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/linux/drivers/scsi/isci/
H A Dhost.c7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
100 * NORMALIZE_PUT_POINTER() -
110 * NORMALIZE_EVENT_POINTER() -
122 * NORMALIZE_GET_POINTER() -
131 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
137 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
140 * COMPLETION_QUEUE_CYCLE_BIT() -
152 sm->initial_state_id = initial_state; in sci_init_sm()
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/linux/drivers/i2c/busses/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
73 will be called i2c-amd8111.
83 be called i2c-amd-mp2-pci and i2c-amd-mp2-plat.
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/linux/drivers/gpu/drm/display/
H A Ddrm_dp_helper.c76 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
230 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_clock_recovery_delay_us()
231 aux->name, rd_interval); in __8b10b_clock_recovery_delay_us()
242 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_channel_eq_delay_us()
243 aux->name, rd_interval); in __8b10b_channel_eq_delay_us()
255 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", in __128b132b_channel_eq_delay_us()
256 aux->name, rd_interval); in __128b132b_channel_eq_delay_us()
278 * - Clock recovery vs. channel equalization
279 * - DPRX vs. LTTPR
280 * - 128b/132b vs. 8b/10b
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/linux/drivers/gpu/drm/i915/
H A Di915_reg.h18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
234 * [0-7] @ 0x2000 gen2,gen3
235 * [8-15] @ 0x3000 945,g33,pnv
237 * [0-15] @ 0x3000 gen4,gen5
239 * [0-15] @ 0x100000 gen6,vlv,chv
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