Lines Matching +full:ssc +full:- +full:range
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
234 * [0-7] @ 0x2000 gen2,gen3
235 * [8-15] @ 0x3000 945,g33,pnv
237 * [0-15] @ 0x3000 gen4,gen5
239 * [0-15] @ 0x100000 gen6,vlv,chv
240 * [0-31] @ 0x100000 gen7+
245 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
253 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
282 #define PRB0_BASE (0x2030 - 0x30)
283 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
284 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
285 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
286 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
287 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
288 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
353 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
354 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
446 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
528 /* Enables non-sequential data reads through arbiter
537 /* Arbiter time slice for non-isoch streams */
571 * These defines should cover us well from SNB->HSW with minor exceptions
610 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
736 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
737 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)…
746 /* i830, required in DVO non-gang */
758 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
765 * digital display port. The range is 4 to 13; 10 or more
861 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
862 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
863 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
864 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
865 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
866 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
867 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
868 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
869 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
870 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
871 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
872 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
878 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
879 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
980 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
1162 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1315 * Programmed value is multiplier - 1, up to 5x.
1363 * of the infoframe structure specified by CEA-861. */
1421 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
1423 #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
1424 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
1426 #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
1427 #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
1430 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
1432 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
1461 /* Link training mode - select a suitable mode for each stage */
1485 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1496 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
1549 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1551 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
1567 * Attributes and VB-ID.
1586 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
1589 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
1590 …CONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
1594 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
1597 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
1608 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
1624 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
1625 … TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
1626 …RANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
1627 …RANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
1629 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
1662 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
1685 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
1712 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
1714 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
1847 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
2119 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
2120 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
2121 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
2122 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
2123 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
2231 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
2247 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-lin…
2259 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
2535 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
2544 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
2545 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
2715 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
2768 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
2769 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
2770 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2976 /* south display engine interrupt: CPT - CNP */
3063 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
3064 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
3065 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
3066 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
3067 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
3074 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
3075 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
3076 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
3077 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
3078 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
3085 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
3086 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
3087 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
3088 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
3089 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
3262 /* Per-transcoder DIP controls (PCH) */
3278 /* Per-transcoder DIP controls (VLV) */
3379 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
3402 …CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
3419 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3420 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3454 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
3489 /* SNB A-stepping */
3494 /* SNB B-stepping */
3551 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
3624 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
3627 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
3653 /* These are the 4 32-bit write offset registers for each stream
3660 * HSW - ICL power wells
3664 * - main (HSW_PWR_WELL_CTL[1-4])
3665 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
3666 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
3669 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
3670 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
3671 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
3672 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
3697 /* ICL/TGL - power wells */
3704 /* XE_LPD - power wells */
3756 /* HSW - power well misc debug registers */
3776 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
3779 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
3782 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
3785 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
3786 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
3788 /* Per-pipe DDI Function Control */
3840 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
3920 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
4000 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4017 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4018 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
4176 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
4185 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
4210 (tc_port) - TC_PORT_4 + 21))
4293 /* ADL-P Type C PLL */
4383 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
4427 /* Pipe WM_LINETIME - watermark line time */