Lines Matching +full:ssc +full:- +full:range
76 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
230 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_clock_recovery_delay_us()
231 aux->name, rd_interval); in __8b10b_clock_recovery_delay_us()
242 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", in __8b10b_channel_eq_delay_us()
243 aux->name, rd_interval); in __8b10b_channel_eq_delay_us()
255 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", in __128b132b_channel_eq_delay_us()
256 aux->name, rd_interval); in __128b132b_channel_eq_delay_us()
278 * - Clock recovery vs. channel equalization
279 * - DPRX vs. LTTPR
280 * - 128b/132b vs. 8b/10b
281 * - DPCD rev 1.3 vs. later
330 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", in __read_delay()
331 aux->name); in __read_delay()
361 drm_err(aux->drm_dev, "%s: failed rd interval read\n", in drm_dp_128b132b_read_aux_rd_interval()
362 aux->name); in drm_dp_128b132b_read_aux_rd_interval()
408 * drm_dp_phy_name() - Get the name of the given DP PHY
413 * non-NULL and valid.
447 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; in dp_lttpr_phy_cap()
499 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; in drm_dp_dump_access()
502 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", in drm_dp_dump_access()
503 aux->name, offset, arrow, ret, min(ret, 20), buffer); in drm_dp_dump_access()
505 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", in drm_dp_dump_access()
506 aux->name, offset, arrow, ret); in drm_dp_dump_access()
512 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
516 * Transactions are described using a hardware-independent drm_dp_aux_msg
518 * Both native and I2C-over-AUX transactions are supported.
534 mutex_lock(&aux->hw_mutex); in drm_dp_dpcd_access()
540 if (aux->powered_down) { in drm_dp_dpcd_access()
541 ret = -EBUSY; in drm_dp_dpcd_access()
552 if (ret != 0 && ret != -ETIMEDOUT) { in drm_dp_dpcd_access()
557 ret = aux->transfer(aux, &msg); in drm_dp_dpcd_access()
564 ret = -EPROTO; in drm_dp_dpcd_access()
566 ret = -EIO; in drm_dp_dpcd_access()
578 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", in drm_dp_dpcd_access()
579 aux->name, err); in drm_dp_dpcd_access()
583 mutex_unlock(&aux->hw_mutex); in drm_dp_dpcd_access()
588 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
593 * be used to trigger some side-effect the read access has, like waking up the
594 * sink, without the need for the read-out value.
613 * drm_dp_dpcd_set_powered() - Set whether the DP device is powered
615 * and the function will be a no-op.
629 mutex_lock(&aux->hw_mutex); in drm_dp_dpcd_set_powered()
630 aux->powered_down = !powered; in drm_dp_dpcd_set_powered()
631 mutex_unlock(&aux->hw_mutex); in drm_dp_dpcd_set_powered()
636 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
643 * code on failure. -EIO is returned if the request was NAKed by the sink or
645 * function returns -EPROTO. Errors from the underlying AUX channel transfer
646 * function, with the exception of -EBUSY (which causes the transaction to
659 * gets woken up and subsequently re-enters power save mode. in drm_dp_dpcd_read()
666 if (!aux->is_remote) { in drm_dp_dpcd_read()
672 if (aux->is_remote) in drm_dp_dpcd_read()
684 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
691 * code on failure. -EIO is returned if the request was NAKed by the sink or
693 * function returns -EPROTO. Errors from the underlying AUX channel transfer
694 * function, with the exception of -EBUSY (which causes the transaction to
702 if (aux->is_remote) in drm_dp_dpcd_write()
714 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
730 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
765 DP_LINK_STATUS_SIZE - 1); in drm_dp_dpcd_read_phy_link_status()
770 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); in drm_dp_dpcd_read_phy_link_status()
773 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], in drm_dp_dpcd_read_phy_link_status()
774 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], in drm_dp_dpcd_read_phy_link_status()
775 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); in drm_dp_dpcd_read_phy_link_status()
776 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; in drm_dp_dpcd_read_phy_link_status()
787 return edid && edid->revision >= 4 && in is_edid_digital_input_dp()
788 edid->input & DRM_EDID_INPUT_DIGITAL && in is_edid_digital_input_dp()
789 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; in is_edid_digital_input_dp()
793 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
815 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
850 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
864 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", in drm_dp_send_real_edid_checksum()
865 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); in drm_dp_send_real_edid_checksum()
871 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", in drm_dp_send_real_edid_checksum()
872 aux->name, DP_TEST_REQUEST); in drm_dp_send_real_edid_checksum()
878 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", in drm_dp_send_real_edid_checksum()
879 aux->name); in drm_dp_send_real_edid_checksum()
885 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
886 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); in drm_dp_send_real_edid_checksum()
893 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
894 aux->name, DP_TEST_EDID_CHECKSUM); in drm_dp_send_real_edid_checksum()
900 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", in drm_dp_send_real_edid_checksum()
901 aux->name, DP_TEST_RESPONSE); in drm_dp_send_real_edid_checksum()
941 return -EIO; in drm_dp_read_extended_dpcd_caps()
944 drm_dbg_kms(aux->drm_dev, in drm_dp_read_extended_dpcd_caps()
946 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); in drm_dp_read_extended_dpcd_caps()
953 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_extended_dpcd_caps()
961 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
982 return -EIO; in drm_dp_read_dpcd_caps()
988 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_dpcd_caps()
995 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
1035 return -EIO; in drm_dp_read_downstream_info()
1037 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); in drm_dp_read_downstream_info()
1044 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1072 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1137 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1180 * drm_dp_downstream_max_bpc() - extract downstream facing port max
1237 * drm_dp_downstream_420_passthrough() - determine downstream facing port
1238 * YCbCr 4:2:0 pass-through capability
1268 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1269 * YCbCr 4:4:4->4:2:0 conversion capability
1297 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1298 * RGB->YCbCr conversion capability
1303 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1329 * drm_dp_downstream_mode() - return a mode for downstream facing port
1384 * drm_dp_downstream_id() - identify branch device
1397 * drm_dp_downstream_debug() - debug DP branch devices
1488 * drm_dp_subconnector_type() - get DP branch device type
1506 /* Can be HDMI or DVI-D, DVI-D is a safer option */ in drm_dp_subconnector_type()
1509 /* Can be VGA or DVI-A, VGA is more popular */ in drm_dp_subconnector_type()
1540 * drm_dp_set_subconnector_property - set subconnector for DP connector
1557 drm_object_property_set_value(&connector->base, in drm_dp_set_subconnector_property()
1558 connector->dev->mode_config.dp_subconnector_property, in drm_dp_set_subconnector_property()
1564 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1580 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && in drm_dp_read_sink_count_cap()
1588 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1605 return -EIO; in drm_dp_read_sink_count()
1612 * I2C-over-AUX implementation
1630 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { in drm_dp_i2c_msg_write_status_update()
1631 msg->request &= DP_AUX_I2C_MOT; in drm_dp_i2c_msg_write_status_update()
1632 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; in drm_dp_i2c_msg_write_status_update()
1653 if ((msg->request & DP_AUX_I2C_READ) == 0) in drm_dp_aux_req_duration()
1654 len += msg->size * 8; in drm_dp_aux_req_duration()
1668 if (msg->request & DP_AUX_I2C_READ) in drm_dp_aux_reply_duration()
1669 len += msg->size * 8; in drm_dp_aux_reply_duration()
1692 msg->size * I2C_DATA_LEN + in drm_dp_i2c_msg_duration()
1718 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1721 * Transfer a single I2C-over-AUX message and handle various error conditions,
1742 ret = aux->transfer(aux, msg); in drm_dp_i2c_do_msg()
1744 if (ret == -EBUSY) in drm_dp_i2c_do_msg()
1750 * communicate with a non-existent DisplayPort device). in drm_dp_i2c_do_msg()
1753 if (ret == -ETIMEDOUT) in drm_dp_i2c_do_msg()
1754 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", in drm_dp_i2c_do_msg()
1755 aux->name); in drm_dp_i2c_do_msg()
1757 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", in drm_dp_i2c_do_msg()
1758 aux->name, ret); in drm_dp_i2c_do_msg()
1763 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { in drm_dp_i2c_do_msg()
1766 * For I2C-over-AUX transactions this isn't enough, we in drm_dp_i2c_do_msg()
1772 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", in drm_dp_i2c_do_msg()
1773 aux->name, ret, msg->size); in drm_dp_i2c_do_msg()
1774 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1777 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); in drm_dp_i2c_do_msg()
1781 * more careful with DP-to-legacy adapters where a in drm_dp_i2c_do_msg()
1785 * safe for all use-cases. in drm_dp_i2c_do_msg()
1791 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", in drm_dp_i2c_do_msg()
1792 aux->name, msg->reply); in drm_dp_i2c_do_msg()
1793 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1796 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { in drm_dp_i2c_do_msg()
1802 if (ret != msg->size) in drm_dp_i2c_do_msg()
1807 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", in drm_dp_i2c_do_msg()
1808 aux->name, ret, msg->size); in drm_dp_i2c_do_msg()
1809 aux->i2c_nack_count++; in drm_dp_i2c_do_msg()
1810 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1813 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); in drm_dp_i2c_do_msg()
1818 aux->i2c_defer_count++; in drm_dp_i2c_do_msg()
1827 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", in drm_dp_i2c_do_msg()
1828 aux->name, msg->reply); in drm_dp_i2c_do_msg()
1829 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1833 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); in drm_dp_i2c_do_msg()
1834 return -EREMOTEIO; in drm_dp_i2c_do_msg()
1840 msg->request = (i2c_msg->flags & I2C_M_RD) ? in drm_dp_i2c_msg_set_request()
1842 if (!(i2c_msg->flags & I2C_M_STOP)) in drm_dp_i2c_msg_set_request()
1843 msg->request |= DP_AUX_I2C_MOT; in drm_dp_i2c_msg_set_request()
1853 int err, ret = orig_msg->size; in drm_dp_i2c_drain_msg()
1859 return err == 0 ? -EPROTO : err; in drm_dp_i2c_drain_msg()
1862 drm_dbg_kms(aux->drm_dev, in drm_dp_i2c_drain_msg()
1864 aux->name, msg.size, err); in drm_dp_i2c_drain_msg()
1868 msg.size -= err; in drm_dp_i2c_drain_msg()
1876 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1883 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1888 struct drm_dp_aux *aux = adapter->algo_data; in drm_dp_i2c_xfer()
1894 if (aux->powered_down) in drm_dp_i2c_xfer()
1895 return -EBUSY; in drm_dp_i2c_xfer()
1927 msg.size = min(transfer_size, msgs[i].len - j); in drm_dp_i2c_xfer()
1970 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); in lock_bus()
1975 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); in trylock_bus()
1980 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); in unlock_bus()
2005 if (count == aux->crc_count) in drm_dp_aux_get_crc()
2006 return -EAGAIN; /* No CRC yet */ in drm_dp_aux_get_crc()
2008 aux->crc_count = count; in drm_dp_aux_get_crc()
2030 if (WARN_ON(!aux->crtc)) in drm_dp_aux_crc_work()
2033 crtc = aux->crtc; in drm_dp_aux_crc_work()
2034 while (crtc->crc.opened) { in drm_dp_aux_crc_work()
2036 if (!crtc->crc.opened) in drm_dp_aux_crc_work()
2040 if (ret == -EAGAIN) { in drm_dp_aux_crc_work()
2045 if (ret == -EAGAIN) { in drm_dp_aux_crc_work()
2046 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", in drm_dp_aux_crc_work()
2047 aux->name, ret); in drm_dp_aux_crc_work()
2050 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); in drm_dp_aux_crc_work()
2062 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2070 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); in drm_dp_remote_aux_init()
2075 * drm_dp_aux_init() - minimally initialise an aux channel
2093 mutex_init(&aux->hw_mutex); in drm_dp_aux_init()
2094 mutex_init(&aux->cec.lock); in drm_dp_aux_init()
2095 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); in drm_dp_aux_init()
2097 aux->ddc.algo = &drm_dp_i2c_algo; in drm_dp_aux_init()
2098 aux->ddc.algo_data = aux; in drm_dp_aux_init()
2099 aux->ddc.retries = 3; in drm_dp_aux_init()
2101 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; in drm_dp_aux_init()
2106 * drm_dp_aux_register() - initialise and register aux channel
2136 WARN_ON_ONCE(!aux->drm_dev); in drm_dp_aux_register()
2138 if (!aux->ddc.algo) in drm_dp_aux_register()
2141 aux->ddc.owner = THIS_MODULE; in drm_dp_aux_register()
2142 aux->ddc.dev.parent = aux->dev; in drm_dp_aux_register()
2144 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), in drm_dp_aux_register()
2145 sizeof(aux->ddc.name)); in drm_dp_aux_register()
2151 ret = i2c_add_adapter(&aux->ddc); in drm_dp_aux_register()
2162 * drm_dp_aux_unregister() - unregister an AUX adapter
2168 i2c_del_adapter(&aux->ddc); in drm_dp_aux_unregister()
2175 * drm_dp_psr_setup_time() - PSR setup in time usec
2197 return -EINVAL; in drm_dp_psr_setup_time()
2206 * drm_dp_start_crc() - start capture of frame CRCs
2225 aux->crc_count = 0; in drm_dp_start_crc()
2226 aux->crtc = crtc; in drm_dp_start_crc()
2227 schedule_work(&aux->crc_work); in drm_dp_start_crc()
2234 * drm_dp_stop_crc() - stop capture of frame CRCs
2252 flush_work(&aux->crc_work); in drm_dp_stop_crc()
2253 aux->crtc = NULL; in drm_dp_stop_crc()
2275 /* LG LP140WF6-SPM1 eDP panel */
2312 if (quirk->is_branch != is_branch) in drm_dp_get_quirks()
2315 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) in drm_dp_get_quirks()
2318 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && in drm_dp_get_quirks()
2319 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) in drm_dp_get_quirks()
2322 quirks |= quirk->quirks; in drm_dp_get_quirks()
2344 const struct drm_dp_dpcd_ident *ident = &desc->ident; in drm_dp_dump_desc()
2346 drm_dbg_kms(aux->drm_dev, in drm_dp_dump_desc()
2347 "%s: %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", in drm_dp_dump_desc()
2348 aux->name, device_name, in drm_dp_dump_desc()
2349 (int)sizeof(ident->oui), ident->oui, in drm_dp_dump_desc()
2350 (int)strnlen(ident->device_id, sizeof(ident->device_id)), ident->device_id, in drm_dp_dump_desc()
2351 ident->hw_rev >> 4, ident->hw_rev & 0xf, in drm_dp_dump_desc()
2352 ident->sw_major_rev, ident->sw_minor_rev, in drm_dp_dump_desc()
2353 desc->quirks); in drm_dp_dump_desc()
2357 * drm_dp_read_desc - read sink/branch descriptor from DPCD
2370 struct drm_dp_dpcd_ident *ident = &desc->ident; in drm_dp_read_desc()
2378 desc->quirks = drm_dp_get_quirks(ident, is_branch); in drm_dp_read_desc()
2387 * drm_dp_dump_lttpr_desc - read and dump the DPCD descriptor for an LTTPR PHY
2401 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT)) in drm_dp_dump_lttpr_desc()
2402 return -EINVAL; in drm_dp_dump_lttpr_desc()
2415 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2422 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_bpp_incr()
2442 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2460 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2472 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2501 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2517 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_line_buf_depth()
2545 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2565 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_supported_input_bpcs()
2588 * corrupted values when reading from the 0xF0000- range with a block in drm_dp_read_lttpr_regs()
2609 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2629 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2652 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; in dp_lttpr_common_cap()
2656 * drm_dp_lttpr_count - get the number of detected LTTPRs
2662 * -ERANGE if more than supported number (8) of LTTPRs are detected
2663 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2674 return 8 - ilog2(count); in drm_dp_lttpr_count()
2676 return -ERANGE; in drm_dp_lttpr_count()
2678 return -EINVAL; in drm_dp_lttpr_count()
2684 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2698 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2712 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2728 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2732 * pre-emphasis level 3.
2744 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2759 data->link_rate = drm_dp_bw_code_to_link_rate(rate); in drm_dp_get_phy_test_pattern()
2764 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; in drm_dp_get_phy_test_pattern()
2767 data->enhanced_frame_cap = true; in drm_dp_get_phy_test_pattern()
2769 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); in drm_dp_get_phy_test_pattern()
2773 switch (data->phy_pattern) { in drm_dp_get_phy_test_pattern()
2776 &data->custom80, sizeof(data->custom80)); in drm_dp_get_phy_test_pattern()
2783 &data->hbr2_reset, in drm_dp_get_phy_test_pattern()
2784 sizeof(data->hbr2_reset)); in drm_dp_get_phy_test_pattern()
2794 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2807 test_pattern = data->phy_pattern; in drm_dp_set_phy_test_pattern()
2816 for (i = 0; i < data->num_lanes; i++) { in drm_dp_set_phy_test_pattern()
2910 return "DCI-P3"; in dp_colorimetry_get_name()
2958 return "VESA range"; in dp_dynamic_range_get_name()
2960 return "CTA range"; in dp_dynamic_range_get_name()
2987 vsc->revision, vsc->length); in drm_dp_vsc_sdp_log()
2989 dp_pixelformat_get_name(vsc->pixelformat)); in drm_dp_vsc_sdp_log()
2991 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); in drm_dp_vsc_sdp_log()
2992 drm_printf(p, " bpc: %u\n", vsc->bpc); in drm_dp_vsc_sdp_log()
2993 drm_printf(p, " dynamic range: %s\n", in drm_dp_vsc_sdp_log()
2994 dp_dynamic_range_get_name(vsc->dynamic_range)); in drm_dp_vsc_sdp_log()
2996 dp_content_type_get_name(vsc->content_type)); in drm_dp_vsc_sdp_log()
3003 as_sdp->revision, as_sdp->length); in drm_dp_as_sdp_log()
3004 drm_printf(p, " vtotal: %d\n", as_sdp->vtotal); in drm_dp_as_sdp_log()
3005 drm_printf(p, " target_rr: %d\n", as_sdp->target_rr); in drm_dp_as_sdp_log()
3006 drm_printf(p, " duration_incr_ms: %d\n", as_sdp->duration_incr_ms); in drm_dp_as_sdp_log()
3007 drm_printf(p, " duration_decr_ms: %d\n", as_sdp->duration_decr_ms); in drm_dp_as_sdp_log()
3008 drm_printf(p, " operation_mode: %d\n", as_sdp->mode); in drm_dp_as_sdp_log()
3013 * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
3028 drm_dbg_dp(aux->drm_dev, in drm_dp_as_sdp_supported()
3038 * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
3052 drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n"); in drm_dp_vsc_sdp_supported()
3061 * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp
3063 * table 2-118 - table 2-120 in DP 1.4a specification
3076 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 in drm_dp_vsc_sdp_pack()
3079 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ in drm_dp_vsc_sdp_pack()
3080 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ in drm_dp_vsc_sdp_pack()
3081 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ in drm_dp_vsc_sdp_pack()
3082 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ in drm_dp_vsc_sdp_pack()
3084 if (vsc->revision == 0x6) { in drm_dp_vsc_sdp_pack()
3085 sdp->db[0] = 1; in drm_dp_vsc_sdp_pack()
3086 sdp->db[3] = 1; in drm_dp_vsc_sdp_pack()
3093 if (!(vsc->revision == 0x5 || vsc->revision == 0x7)) in drm_dp_vsc_sdp_pack()
3098 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ in drm_dp_vsc_sdp_pack()
3099 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ in drm_dp_vsc_sdp_pack()
3101 switch (vsc->bpc) { in drm_dp_vsc_sdp_pack()
3106 sdp->db[17] = 0x1; /* DB17[3:0] */ in drm_dp_vsc_sdp_pack()
3109 sdp->db[17] = 0x2; in drm_dp_vsc_sdp_pack()
3112 sdp->db[17] = 0x3; in drm_dp_vsc_sdp_pack()
3115 sdp->db[17] = 0x4; in drm_dp_vsc_sdp_pack()
3118 WARN(1, "Missing case %d\n", vsc->bpc); in drm_dp_vsc_sdp_pack()
3119 return -EINVAL; in drm_dp_vsc_sdp_pack()
3122 /* Dynamic Range and Component Bit Depth */ in drm_dp_vsc_sdp_pack()
3123 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) in drm_dp_vsc_sdp_pack()
3124 sdp->db[17] |= 0x80; /* DB17[7] */ in drm_dp_vsc_sdp_pack()
3127 sdp->db[18] = vsc->content_type & 0x7; in drm_dp_vsc_sdp_pack()
3135 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
3174 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
3196 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
3218 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3267 return -EINVAL; in drm_dp_pcon_frl_configure_1()
3279 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3309 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3327 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3341 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", in drm_dp_pcon_frl_enable()
3342 aux->name); in drm_dp_pcon_frl_enable()
3343 return -EINVAL; in drm_dp_pcon_frl_enable()
3355 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3374 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3404 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3416 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; in drm_dp_pcon_hdmi_frl_link_error_count()
3418 for (i = 0; i < hdmi->max_lanes; i++) { in drm_dp_pcon_hdmi_frl_link_error_count()
3437 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", in drm_dp_pcon_hdmi_frl_link_error_count()
3438 aux->name, num_error, i); in drm_dp_pcon_hdmi_frl_link_error_count()
3444 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3454 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_enc_is_dsc_1_2()
3466 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3475 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slices()
3476 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slices()
3504 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3513 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_max_slice_width()
3520 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3529 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; in drm_dp_pcon_dsc_bpp_incr()
3573 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3592 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3616 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3647 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3649 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3676 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3693 if (!bl->aux_set) in drm_edp_backlight_set_level()
3696 if (bl->lsb_reg_used) { in drm_edp_backlight_set_level()
3705 drm_err(aux->drm_dev, in drm_edp_backlight_set_level()
3707 aux->name, ret); in drm_edp_backlight_set_level()
3708 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_level()
3723 if (!bl->aux_enable) in drm_edp_backlight_set_enable()
3728 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", in drm_edp_backlight_set_enable()
3729 aux->name, ret); in drm_edp_backlight_set_enable()
3730 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_enable()
3739 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", in drm_edp_backlight_set_enable()
3740 aux->name, ret); in drm_edp_backlight_set_enable()
3741 return ret < 0 ? ret : -EIO; in drm_edp_backlight_set_enable()
3748 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3758 * that the driver handle enabling/disabling the panel through implementation-specific means using
3760 * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3771 if (bl->aux_set) in drm_edp_backlight_enable()
3776 if (bl->pwmgen_bit_count) { in drm_edp_backlight_enable()
3777 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); in drm_edp_backlight_enable()
3779 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", in drm_edp_backlight_enable()
3780 aux->name, ret); in drm_edp_backlight_enable()
3783 if (bl->pwm_freq_pre_divider) { in drm_edp_backlight_enable()
3784 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); in drm_edp_backlight_enable()
3786 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_enable()
3788 aux->name, ret); in drm_edp_backlight_enable()
3795 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", in drm_edp_backlight_enable()
3796 aux->name, ret); in drm_edp_backlight_enable()
3797 return ret < 0 ? ret : -EIO; in drm_edp_backlight_enable()
3812 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3819 * that the driver handle enabling/disabling the panel through implementation-specific means using
3821 * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3824 * Returns: %0 on success or no-op, negative error code on failure.
3846 if (!bl->aux_set) in drm_edp_backlight_probe_max()
3851 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", in drm_edp_backlight_probe_max()
3852 aux->name, ret); in drm_edp_backlight_probe_max()
3853 return -ENODEV; in drm_edp_backlight_probe_max()
3857 bl->max = (1 << pn) - 1; in drm_edp_backlight_probe_max()
3864 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the in drm_edp_backlight_probe_max()
3866 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the in drm_edp_backlight_probe_max()
3871 * Note that, if F x P is out of supported range, the maximum value or minimum value will in drm_edp_backlight_probe_max()
3878 * - Pn is in the range of Pn_min and Pn_max in drm_edp_backlight_probe_max()
3879 * - F is in the range of 1 and 255 in drm_edp_backlight_probe_max()
3880 * - FxP is within 25% of desired value. in drm_edp_backlight_probe_max()
3885 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", in drm_edp_backlight_probe_max()
3886 aux->name, ret); in drm_edp_backlight_probe_max()
3891 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", in drm_edp_backlight_probe_max()
3892 aux->name, ret); in drm_edp_backlight_probe_max()
3902 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_probe_max()
3903 "%s: Driver defined backlight frequency (%d) out of range\n", in drm_edp_backlight_probe_max()
3904 aux->name, driver_pwm_freq_hz); in drm_edp_backlight_probe_max()
3908 for (pn = pn_max; pn >= pn_min; pn--) { in drm_edp_backlight_probe_max()
3917 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", in drm_edp_backlight_probe_max()
3918 aux->name, ret); in drm_edp_backlight_probe_max()
3921 bl->pwmgen_bit_count = pn; in drm_edp_backlight_probe_max()
3922 bl->max = (1 << pn) - 1; in drm_edp_backlight_probe_max()
3925 bl->pwm_freq_pre_divider = f; in drm_edp_backlight_probe_max()
3926 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", in drm_edp_backlight_probe_max()
3927 aux->name, driver_pwm_freq_hz); in drm_edp_backlight_probe_max()
3943 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", in drm_edp_backlight_probe_state()
3944 aux->name, ret); in drm_edp_backlight_probe_state()
3945 return ret < 0 ? ret : -EIO; in drm_edp_backlight_probe_state()
3949 if (!bl->aux_set) in drm_edp_backlight_probe_state()
3953 int size = 1 + bl->lsb_reg_used; in drm_edp_backlight_probe_state()
3957 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", in drm_edp_backlight_probe_state()
3958 aux->name, ret); in drm_edp_backlight_probe_state()
3959 return ret < 0 ? ret : -EIO; in drm_edp_backlight_probe_state()
3962 if (bl->lsb_reg_used) in drm_edp_backlight_probe_state()
3972 return bl->max; in drm_edp_backlight_probe_state()
3976 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3988 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
4001 bl->aux_enable = true; in drm_edp_backlight_init()
4003 bl->aux_set = true; in drm_edp_backlight_init()
4005 bl->lsb_reg_used = true; in drm_edp_backlight_init()
4008 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { in drm_edp_backlight_init()
4009 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
4011 aux->name); in drm_edp_backlight_init()
4012 return -EINVAL; in drm_edp_backlight_init()
4024 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
4026 aux->name, bl->aux_set, bl->aux_enable, *current_mode); in drm_edp_backlight_init()
4027 if (bl->aux_set) { in drm_edp_backlight_init()
4028 drm_dbg_kms(aux->drm_dev, in drm_edp_backlight_init()
4030 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, in drm_edp_backlight_init()
4031 bl->lsb_reg_used); in drm_edp_backlight_init()
4048 if (!bl->enabled) { in dp_aux_backlight_update_status()
4049 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); in dp_aux_backlight_update_status()
4050 bl->enabled = true; in dp_aux_backlight_update_status()
4053 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); in dp_aux_backlight_update_status()
4055 if (bl->enabled) { in dp_aux_backlight_update_status()
4056 drm_edp_backlight_disable(bl->aux, &bl->info); in dp_aux_backlight_update_status()
4057 bl->enabled = false; in dp_aux_backlight_update_status()
4069 * drm_panel_dp_aux_backlight - create and use DP AUX backlight
4101 if (!panel || !panel->dev || !aux) in drm_panel_dp_aux_backlight()
4102 return -EINVAL; in drm_panel_dp_aux_backlight()
4110 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); in drm_panel_dp_aux_backlight()
4114 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); in drm_panel_dp_aux_backlight()
4116 return -ENOMEM; in drm_panel_dp_aux_backlight()
4118 bl->aux = aux; in drm_panel_dp_aux_backlight()
4120 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, in drm_panel_dp_aux_backlight()
4127 props.max_brightness = bl->info.max; in drm_panel_dp_aux_backlight()
4129 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", in drm_panel_dp_aux_backlight()
4130 panel->dev, bl, in drm_panel_dp_aux_backlight()
4132 if (IS_ERR(bl->base)) in drm_panel_dp_aux_backlight()
4133 return PTR_ERR(bl->base); in drm_panel_dp_aux_backlight()
4135 backlight_disable(bl->base); in drm_panel_dp_aux_backlight()
4137 panel->backlight = bl->base; in drm_panel_dp_aux_backlight()
4167 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
4176 * - @lane_count
4177 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
4178 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
4179 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
4180 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
4182 * - @hactive timing
4183 * - @bpp_x16 color depth
4184 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
4209 * SSC downspread and ref clock variation margin: in drm_dp_bw_overhead()
4218 * After each 250 data symbols on 2-4 lanes: in drm_dp_bw_overhead()
4222 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks: in drm_dp_bw_overhead()
4256 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4261 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4267 * Returns the efficiency in the 100%/coding-overhead% ratio in
4285 * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
4297 * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
4298 * which in turn can encapsulate an MST link with its own limit - with each