Lines Matching +full:ssc +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
65 int ret = -EINVAL; in _omap3_wait_dpll_status()
68 dd = clk->dpll_data; in _omap3_wait_dpll_status()
69 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status()
71 state <<= __ffs(dd->idlest_mask); in _omap3_wait_dpll_status()
73 while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
98 fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n; in _omap3_dpll_compute_freqsel()
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
136 * allotted, or DPLL3 was passed in, return -EINVAL.
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
147 dd = clk->dpll_data; in _omap3_noncore_dpll_lock()
148 state <<= __ffs(dd->idlest_mask); in _omap3_noncore_dpll_lock()
151 if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) == in _omap3_noncore_dpll_lock()
172 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
175 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
181 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
182 * return -EINVAL.
189 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) in _omap3_noncore_dpll_bypass()
190 return -EINVAL; in _omap3_noncore_dpll_bypass()
192 pr_debug("clock: configuring DPLL %s for low-power bypass\n", in _omap3_noncore_dpll_bypass()
193 clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_bypass()
208 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
211 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
214 * low-power stop, return -EINVAL; otherwise, return 0.
220 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) in _omap3_noncore_dpll_stop()
221 return -EINVAL; in _omap3_noncore_dpll_stop()
223 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_stop()
236 * _lookup_dco - Lookup DCO used by j-type DPLL
242 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
245 * out in non-multi-OMAP builds for those chips?
251 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); in _lookup_dco()
261 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
263 * @sd_div: target sigma-delta divider
267 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
270 * out in non-multi-OMAP builds for those chips?
277 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); in _lookup_sddiv()
280 * target sigma-delta to near 250MHz in _lookup_sddiv()
295 * omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers
303 struct dpll_data *dd = clk->dpll_data; in omap3_noncore_dpll_ssc_program()
308 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_ssc_program()
310 if (dd->ssc_modfreq && dd->ssc_deltam) { in omap3_noncore_dpll_ssc_program()
311 ctrl |= dd->ssc_enable_mask; in omap3_noncore_dpll_ssc_program()
313 if (dd->ssc_downspread) in omap3_noncore_dpll_ssc_program()
314 ctrl |= dd->ssc_downspread_mask; in omap3_noncore_dpll_ssc_program()
316 ctrl &= ~dd->ssc_downspread_mask; in omap3_noncore_dpll_ssc_program()
318 ref_rate = clk_hw_get_rate(dd->clk_ref); in omap3_noncore_dpll_ssc_program()
320 (ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq); in omap3_noncore_dpll_ssc_program()
321 if (dd->ssc_modfreq > (ref_rate / 70)) in omap3_noncore_dpll_ssc_program()
322 pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n", in omap3_noncore_dpll_ssc_program()
323 __clk_get_name(clk->hw.clk), ref_rate / 70); in omap3_noncore_dpll_ssc_program()
334 v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg); in omap3_noncore_dpll_ssc_program()
335 v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask); in omap3_noncore_dpll_ssc_program()
336 v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask); in omap3_noncore_dpll_ssc_program()
337 v |= exponent << __ffs(dd->ssc_modfreq_exp_mask); in omap3_noncore_dpll_ssc_program()
338 ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg); in omap3_noncore_dpll_ssc_program()
340 deltam_step = dd->last_rounded_m * dd->ssc_deltam; in omap3_noncore_dpll_ssc_program()
342 if (dd->ssc_downspread) in omap3_noncore_dpll_ssc_program()
345 deltam_step <<= __ffs(dd->ssc_deltam_int_mask); in omap3_noncore_dpll_ssc_program()
351 deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >> in omap3_noncore_dpll_ssc_program()
352 __ffs(dd->ssc_deltam_int_mask); in omap3_noncore_dpll_ssc_program()
353 if (deltam_step & dd->ssc_deltam_frac_mask) in omap3_noncore_dpll_ssc_program()
356 if ((dd->ssc_downspread && in omap3_noncore_dpll_ssc_program()
357 ((dd->last_rounded_m - (2 * deltam_ceil)) < 20 || in omap3_noncore_dpll_ssc_program()
358 dd->last_rounded_m > 2045)) || in omap3_noncore_dpll_ssc_program()
359 ((dd->last_rounded_m - deltam_ceil) < 20 || in omap3_noncore_dpll_ssc_program()
360 (dd->last_rounded_m + deltam_ceil) > 2045)) in omap3_noncore_dpll_ssc_program()
361 pr_warn("clock: SSC multiplier of DPLL %s is out of range\n", in omap3_noncore_dpll_ssc_program()
362 __clk_get_name(clk->hw.clk)); in omap3_noncore_dpll_ssc_program()
364 v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg); in omap3_noncore_dpll_ssc_program()
365 v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask); in omap3_noncore_dpll_ssc_program()
366 v |= deltam_step << __ffs(dd->ssc_deltam_int_mask | in omap3_noncore_dpll_ssc_program()
367 dd->ssc_deltam_frac_mask); in omap3_noncore_dpll_ssc_program()
368 ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg); in omap3_noncore_dpll_ssc_program()
370 ctrl &= ~dd->ssc_enable_mask; in omap3_noncore_dpll_ssc_program()
373 ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg); in omap3_noncore_dpll_ssc_program()
377 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
382 * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
386 struct dpll_data *dd = clk->dpll_data; in omap3_noncore_dpll_program()
398 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { in omap3_noncore_dpll_program()
399 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
400 v &= ~dd->freqsel_mask; in omap3_noncore_dpll_program()
401 v |= freqsel << __ffs(dd->freqsel_mask); in omap3_noncore_dpll_program()
402 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program()
406 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_noncore_dpll_program()
409 if (dd->dcc_mask) { in omap3_noncore_dpll_program()
410 if (dd->last_rounded_rate >= dd->dcc_rate) in omap3_noncore_dpll_program()
411 v |= dd->dcc_mask; /* Enable DCC */ in omap3_noncore_dpll_program()
413 v &= ~dd->dcc_mask; /* Disable DCC */ in omap3_noncore_dpll_program()
416 v &= ~(dd->mult_mask | dd->div1_mask); in omap3_noncore_dpll_program()
417 v |= dd->last_rounded_m << __ffs(dd->mult_mask); in omap3_noncore_dpll_program()
418 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); in omap3_noncore_dpll_program()
421 if (dd->dco_mask) { in omap3_noncore_dpll_program()
422 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); in omap3_noncore_dpll_program()
423 v &= ~(dd->dco_mask); in omap3_noncore_dpll_program()
424 v |= dco << __ffs(dd->dco_mask); in omap3_noncore_dpll_program()
426 if (dd->sddiv_mask) { in omap3_noncore_dpll_program()
427 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, in omap3_noncore_dpll_program()
428 dd->last_rounded_n); in omap3_noncore_dpll_program()
429 v &= ~(dd->sddiv_mask); in omap3_noncore_dpll_program()
430 v |= sd_div << __ffs(dd->sddiv_mask); in omap3_noncore_dpll_program()
434 * Errata i810 - DPLL controller can get stuck while transitioning in omap3_noncore_dpll_program()
438 * before doing the M/N re-program. in omap3_noncore_dpll_program()
440 errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810; in omap3_noncore_dpll_program()
452 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg); in omap3_noncore_dpll_program()
454 /* Set 4X multiplier and low-power mode */ in omap3_noncore_dpll_program()
455 if (dd->m4xen_mask || dd->lpmode_mask) { in omap3_noncore_dpll_program()
456 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()
458 if (dd->m4xen_mask) { in omap3_noncore_dpll_program()
459 if (dd->last_rounded_m4xen) in omap3_noncore_dpll_program()
460 v |= dd->m4xen_mask; in omap3_noncore_dpll_program()
462 v &= ~dd->m4xen_mask; in omap3_noncore_dpll_program()
465 if (dd->lpmode_mask) { in omap3_noncore_dpll_program()
466 if (dd->last_rounded_lpmode) in omap3_noncore_dpll_program()
467 v |= dd->lpmode_mask; in omap3_noncore_dpll_program()
469 v &= ~dd->lpmode_mask; in omap3_noncore_dpll_program()
472 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program()
475 if (dd->ssc_enable_mask) in omap3_noncore_dpll_program()
480 /* REVISIT: Set ramp-up delay? */ in omap3_noncore_dpll_program()
493 * omap3_dpll_recalc - recalculate DPLL rate
506 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
509 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
512 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
519 * support low-power stop, or if the DPLL took too long to enter
520 * bypass or lock, return -EINVAL; otherwise, return 0.
529 dd = clk->dpll_data; in omap3_noncore_dpll_enable()
531 return -EINVAL; in omap3_noncore_dpll_enable()
533 if (clk->clkdm) { in omap3_noncore_dpll_enable()
534 r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap3_noncore_dpll_enable()
539 clk->clkdm_name, r); in omap3_noncore_dpll_enable()
546 if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) { in omap3_noncore_dpll_enable()
547 WARN_ON(parent != dd->clk_bypass); in omap3_noncore_dpll_enable()
550 WARN_ON(parent != dd->clk_ref); in omap3_noncore_dpll_enable()
558 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
561 * Instructs a non-CORE DPLL to enter low-power stop. This function is
569 if (clk->clkdm) in omap3_noncore_dpll_disable()
570 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in omap3_noncore_dpll_disable()
573 /* Non-CORE DPLL rate set code */
576 * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
582 * locked, calculates the M,N values for the DPLL via round-rate.
591 if (!req->rate) in omap3_noncore_dpll_determine_rate()
592 return -EINVAL; in omap3_noncore_dpll_determine_rate()
594 dd = clk->dpll_data; in omap3_noncore_dpll_determine_rate()
596 return -EINVAL; in omap3_noncore_dpll_determine_rate()
598 if (clk_hw_get_rate(dd->clk_bypass) == req->rate && in omap3_noncore_dpll_determine_rate()
599 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { in omap3_noncore_dpll_determine_rate()
600 req->best_parent_hw = dd->clk_bypass; in omap3_noncore_dpll_determine_rate()
602 req->rate = omap2_dpll_round_rate(hw, req->rate, in omap3_noncore_dpll_determine_rate()
603 &req->best_parent_rate); in omap3_noncore_dpll_determine_rate()
604 req->best_parent_hw = dd->clk_ref; in omap3_noncore_dpll_determine_rate()
607 req->best_parent_rate = req->rate; in omap3_noncore_dpll_determine_rate()
613 * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
626 return -EINVAL; in omap3_noncore_dpll_set_parent()
637 * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
656 return -EINVAL; in omap3_noncore_dpll_set_rate()
658 dd = clk->dpll_data; in omap3_noncore_dpll_set_rate()
660 return -EINVAL; in omap3_noncore_dpll_set_rate()
662 if (clk_hw_get_parent(hw) != dd->clk_ref) in omap3_noncore_dpll_set_rate()
663 return -EINVAL; in omap3_noncore_dpll_set_rate()
665 if (dd->last_rounded_rate == 0) in omap3_noncore_dpll_set_rate()
666 return -EINVAL; in omap3_noncore_dpll_set_rate()
669 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { in omap3_noncore_dpll_set_rate()
670 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); in omap3_noncore_dpll_set_rate()
683 * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
687 * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
703 return -EINVAL; in omap3_noncore_dpll_set_rate_and_parent()
706 * clk-ref at index[0], in which case we only need to set rate, in omap3_noncore_dpll_set_rate_and_parent()
708 * With clk-bypass case we only need to change parent. in omap3_noncore_dpll_set_rate_and_parent()
721 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
725 * -EINVAL if passed a null pointer or if the struct clk does not
733 if (!clk || !clk->dpll_data) in omap3_dpll_autoidle_read()
734 return -EINVAL; in omap3_dpll_autoidle_read()
736 dd = clk->dpll_data; in omap3_dpll_autoidle_read()
738 if (!dd->autoidle_mask) in omap3_dpll_autoidle_read()
739 return -EINVAL; in omap3_dpll_autoidle_read()
741 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_autoidle_read()
742 v &= dd->autoidle_mask; in omap3_dpll_autoidle_read()
743 v >>= __ffs(dd->autoidle_mask); in omap3_dpll_autoidle_read()
749 * omap3_dpll_allow_idle - enable DPLL autoidle bits
754 * OMAP3430. The DPLL will enter low-power stop when its downstream
762 if (!clk || !clk->dpll_data) in omap3_dpll_allow_idle()
765 dd = clk->dpll_data; in omap3_dpll_allow_idle()
767 if (!dd->autoidle_mask) in omap3_dpll_allow_idle()
771 * REVISIT: CORE DPLL can optionally enter low-power bypass in omap3_dpll_allow_idle()
775 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_allow_idle()
776 v &= ~dd->autoidle_mask; in omap3_dpll_allow_idle()
777 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); in omap3_dpll_allow_idle()
778 ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg); in omap3_dpll_allow_idle()
782 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
792 if (!clk || !clk->dpll_data) in omap3_dpll_deny_idle()
795 dd = clk->dpll_data; in omap3_dpll_deny_idle()
797 if (!dd->autoidle_mask) in omap3_dpll_deny_idle()
800 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_deny_idle()
801 v &= ~dd->autoidle_mask; in omap3_dpll_deny_idle()
802 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); in omap3_dpll_deny_idle()
803 ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg); in omap3_dpll_deny_idle()
821 } while (pclk && !pclk->dpll_data); in omap3_find_clkoutx2_dpll()
833 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
856 dd = pclk->dpll_data; in omap3_clkoutx2_recalc()
858 WARN_ON(!dd->enable_mask); in omap3_clkoutx2_recalc()
860 v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc()
861 v >>= __ffs(dd->enable_mask); in omap3_clkoutx2_recalc()
862 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) in omap3_clkoutx2_recalc()
870 * omap3_core_dpll_save_context - Save the m and n values of the divider
882 dd = clk->dpll_data; in omap3_core_dpll_save_context()
884 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_core_dpll_save_context()
885 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask); in omap3_core_dpll_save_context()
887 if (clk->context == DPLL_LOCKED) { in omap3_core_dpll_save_context()
888 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_core_dpll_save_context()
889 dd->last_rounded_m = (v & dd->mult_mask) >> in omap3_core_dpll_save_context()
890 __ffs(dd->mult_mask); in omap3_core_dpll_save_context()
891 dd->last_rounded_n = ((v & dd->div1_mask) >> in omap3_core_dpll_save_context()
892 __ffs(dd->div1_mask)) + 1; in omap3_core_dpll_save_context()
899 * omap3_core_dpll_restore_context - restore the m and n values of the divider
911 dd = clk->dpll_data; in omap3_core_dpll_restore_context()
913 if (clk->context == DPLL_LOCKED) { in omap3_core_dpll_restore_context()
917 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_core_dpll_restore_context()
918 v &= ~(dd->mult_mask | dd->div1_mask); in omap3_core_dpll_restore_context()
919 v |= dd->last_rounded_m << __ffs(dd->mult_mask); in omap3_core_dpll_restore_context()
920 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); in omap3_core_dpll_restore_context()
921 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg); in omap3_core_dpll_restore_context()
926 _omap3_dpll_write_clken(clk, clk->context); in omap3_core_dpll_restore_context()
931 * omap3_noncore_dpll_save_context - Save the m and n values of the divider
943 dd = clk->dpll_data; in omap3_noncore_dpll_save_context()
945 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_save_context()
946 clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask); in omap3_noncore_dpll_save_context()
948 if (clk->context == DPLL_LOCKED) { in omap3_noncore_dpll_save_context()
949 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_noncore_dpll_save_context()
950 dd->last_rounded_m = (v & dd->mult_mask) >> in omap3_noncore_dpll_save_context()
951 __ffs(dd->mult_mask); in omap3_noncore_dpll_save_context()
952 dd->last_rounded_n = ((v & dd->div1_mask) >> in omap3_noncore_dpll_save_context()
953 __ffs(dd->div1_mask)) + 1; in omap3_noncore_dpll_save_context()
960 * omap3_noncore_dpll_restore_context - restore the m and n values of the divider
972 dd = clk->dpll_data; in omap3_noncore_dpll_restore_context()
974 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_restore_context()
975 mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_noncore_dpll_restore_context()
977 if (clk->context == ((ctrl & dd->enable_mask) >> in omap3_noncore_dpll_restore_context()
978 __ffs(dd->enable_mask)) && in omap3_noncore_dpll_restore_context()
979 dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >> in omap3_noncore_dpll_restore_context()
980 __ffs(dd->mult_mask)) && in omap3_noncore_dpll_restore_context()
981 dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >> in omap3_noncore_dpll_restore_context()
982 __ffs(dd->div1_mask)) + 1) { in omap3_noncore_dpll_restore_context()
987 if (clk->context == DPLL_LOCKED) in omap3_noncore_dpll_restore_context()
990 _omap3_dpll_write_clken(clk, clk->context); in omap3_noncore_dpll_restore_context()
993 /* OMAP3/4 non-CORE DPLL clkops */
1000 * omap3_dpll4_set_rate - set rate for omap3 per-dpll
1005 * Check if the current SoC supports the per-dpll reprogram operation
1006 * or not, and then do the rate change if supported. Returns -EINVAL
1014 * According to the 12-5 CDP code from TI, "Limitation 2.5" in omap3_dpll4_set_rate()
1018 if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { in omap3_dpll4_set_rate()
1020 return -EINVAL; in omap3_dpll4_set_rate()
1027 * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
1031 * @index: parent index, 0 - reference clock, 1 - bypass clock
1033 * Check if the current SoC support the per-dpll reprogram operation
1035 * -EINVAL if not supported, 0 for success, and potential error codes
1041 if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { in omap3_dpll4_set_rate_and_parent()
1043 return -EINVAL; in omap3_dpll4_set_rate_and_parent()
1088 dd = clk->dpll_data; in omap3_dpll5_apply_errata()
1089 dd->last_rounded_m = d->m; in omap3_dpll5_apply_errata()
1090 dd->last_rounded_n = d->n; in omap3_dpll5_apply_errata()
1091 dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n); in omap3_dpll5_apply_errata()
1098 * omap3_dpll5_set_rate - set rate for omap3 dpll5