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/linux/drivers/hid/
H A Dhid-saitek.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Fixes the HID report descriptor by removing a non-existent axis and
7 * clearing the constant bit on the input reports for buttons and d-pad.
8 * (This module is based on "hid-ortek".)
25 #include "hid-ids.h"
39 unsigned long quirks = id->driver_data; in saitek_probe()
40 struct saitek_sc *ssc; in saitek_probe() local
43 ssc = devm_kzalloc(&hdev->dev, sizeof(*ssc), GFP_KERNEL); in saitek_probe()
44 if (ssc == NULL) { in saitek_probe()
46 return -ENOMEM; in saitek_probe()
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/linux/include/linux/
H A Datmel-ssc.h1 /* SPDX-License-Identifier: GPL-2.0 */
28 void ssc_free(struct ssc_device *ssc);
30 /* SSC register offsets */
32 /* SSC Control Register */
45 /* SSC Clock Mode Register */
50 /* SSC Receive Clock Mode Register */
69 /* SSC Receive Frame Mode Register */
78 * The FSLEN_EXT exist on at91sam9rl, at91sam9g10,
92 /* SSC Transmit Clock Mode Register */
109 /* SSC Transmit Frame Mode Register */
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/linux/sound/soc/atmel/
H A Datmel_ssc_dai.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * atmel_ssc_dai.h - ALSA SSC interface for the Atmel SoC
11 * Based on at91-ssc.c by
13 * Based on pxa2xx Platform drivers by
21 #include <linux/atmel-ssc.h>
23 #include "atmel-pcm.h"
25 /* SSC system clock ids */
26 #define ATMEL_SYSCLK_MCK 0 /* SSC uses AT91 MCK as system clock */
28 /* SSC divider ids */
33 * SSC direction masks
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H A Datmel-pcm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * at91-pcm.h - ALSA PCM interface for the Atmel AT91 SoC.
10 * Based on at91-pcm. by:
14 * Based on pxa2xx-pcm.c by:
24 #include <linux/atmel-ssc.h>
40 u32 ssc_enable; /* SSC recv/trans enable */
41 u32 ssc_disable; /* SSC recv/trans disable */
42 u32 ssc_error; /* SSC error conditions */
43 u32 ssc_endx; /* SSC ENDTX or ENDRX */
44 u32 ssc_endbuf; /* SSC TXBUFE or RXBUFF */
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H A Datmel-pcm-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * atmel-pcm-dma.c -- ALSA PCM DMA support for the Atmel SoC.
9 * Based on atmel-pcm by:
18 #include <linux/dma-mapping.h>
20 #include <linux/atmel-ssc.h>
28 #include "atmel-pcm.h"
30 /*--------------------------------------------------------------------------*\
32 \*--------------------------------------------------------------------------*/
47 * atmel_pcm_dma_irq: SSC interrupt handler for DMAENGINE enabled SSC
49 * We use DMAENGINE to send/receive data to/from SSC so this ISR is only to
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H A Datmel-pcm-pdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * atmel-pcm.c -- ALSA PCM interface for the Atmel atmel SoC.
10 * Based on at91-pcm. by:
14 * Based on pxa2xx-pcm.c by:
25 #include <linux/dma-mapping.h>
27 #include <linux/atmel-ssc.h>
34 #include "atmel-pcm.h"
40 struct snd_card *card = rtd->card->snd_card; in atmel_pcm_new()
43 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32)); in atmel_pcm_new()
47 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, in atmel_pcm_new()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Atmel System-on-Chip"
4 depends on HAS_IOMEM
7 the ATMEL SSC interface. You will also need
25 tristate "SoC PCM DAI support for AT91 SSC controller using PDC"
26 depends on ATMEL_SSC
30 Say Y or M if you want to add support for Atmel SSC interface
31 in PDC mode configured using audio-graph-card in device-tree.
34 tristate "SoC PCM DAI support for AT91 SSC controller using DMA"
35 depends on ATMEL_SSC
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H A Dsam9x5_wm8731.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sam9x5_wm8731 -- SoC audio for AT91SAM9X5-based boards
12 * Based on sam9g20_wm8731.c by:
23 #include <sound/soc-dai.h>
24 #include <sound/soc-dapm.h>
32 #define DRV_NAME "sam9x5-snd-wm8731"
39 * Logic for a wm8731 as connected on a at91sam9x5ek based board.
44 struct device *dev = rtd->dev; in sam9x5_wm8731_init()
61 * Audio paths on at91sam9x5ek board:
63 * |A| ------------> | | ---R----> Headphone Jack
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H A Dsam9g20_wm8731.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sam9g20_wm8731 -- SoC audio for AT91SAM9G20-based
11 * Based on ati_b1_wm8731.c by:
14 * Based on corgi.c by:
28 #include <linux/atmel-ssc.h>
36 #include "atmel-pcm.h"
65 * Logic for a wm8731 as connected on a at91sam9g20ek board.
70 struct device *dev = rtd->dev; in at91sam9g20ek_wm8731_init()
83 snd_soc_dapm_nc_pin(&rtd->card->dapm, "Int Mic"); in at91sam9g20ek_wm8731_init()
91 DAILINK_COMP_ARRAY(COMP_CODEC("wm8731.0-001b", "wm8731-hifi")),
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/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ssc-block-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
10 - Michael Srba <Michael.Srba@seznam.cz>
14 need to be turned on in a sequence before communication over the AHB bus
20 The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
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/linux/sound/spi/
H A Dat73c213.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for AT73C213 16-bit stereo DAC connected to Atmel SSC
5 * Copyright (C) 2006-2007 Atmel Norway
14 #include <linux/dma-mapping.h>
27 #include <linux/atmel-ssc.h>
41 0x00, /* 00 - CTRL */
42 0x05, /* 01 - LLIG */
43 0x05, /* 02 - RLIG */
44 0x08, /* 03 - LPMG */
45 0x08, /* 04 - RPMG */
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/linux/Documentation/devicetree/bindings/spi/
H A Dst,ssc-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,ssc-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics SSC SPI Controller
10 The STMicroelectronics SSC SPI controller can be found on STi platforms
15 - Patrice Chotard <patrice.chotard@foss.st.com>
18 - $ref: spi-controller.yaml#
22 const: st,comms-ssc4-spi
30 clock-names:
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/linux/drivers/scsi/isci/
H A Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
229 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
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/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
84 /* ports 1-3 follow after this */
87 /* ports 5-7 follow after this */
91 /* phys 1-3 follow after this */
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/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
13 Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
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/linux/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
34 * lane 0, used for the transmissions on main link.
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
62 * @ssc:
64 * Flag indicating, whether or not to enable spread-spectrum clocking.
67 u8 ssc : 1; member
72 * Flag indicating, whether or not reconfigure link rate and SSC to
91 * and pre-emphasis to requested values. Only lanes specified
/linux/include/linux/clk/
H A Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
29 * struct dpll_data - DPLL registers and integration data
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
45 * @min_divider: minimum valid non-bypass divider value (actual)
46 * @max_divider: maximum valid non-bypass divider value (actual)
56 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
61 * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
62 * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
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/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/iio/pressure/
H A Dhoneywell,hsc030pa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Honeywell TruStability HSC and SSC pressure sensor series
10 support for Honeywell TruStability HSC and SSC digital pressure sensor
17 The vendor calls them "HSC series" and "SSC series". All of them have an
23 pressure-triplet (directly extracted from the part number) or in case it's
27 by the sensor. pmin-pascal and pmax-pascal corespond to the minimum and
30 Please note that in case of an SPI-based sensor, the clock signal should not
34 …-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/bo…
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/linux/drivers/clk/
H A Dclk-renesas-pcie.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
15 #include <linux/clk-provider.h>
56 /* Structure to describe features of a particular 9-series model */
74 * Renesas 9-series i2c regmap
110 return -EIO; in rs9_regmap_i2c_write()
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/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 depends on ARM && OF && CPU_V7
25 depends on HAS_IOMEM
26 depends on ARCH_INTEGRATOR || COMPILE_TEST
30 found on the ARM Integrator AP (Application Platform)
34 depends on ARCH_BRCMSTB || BMIPS_GENERIC
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
43 depends on MIPS_BAIKAL_T1 || COMPILE_TEST
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_quirks.c1 // SPDX-License-Identifier: MIT
14 display->quirks.mask |= BIT(quirk); in intel_set_quirk()
19 intel_dp->quirks.mask |= BIT(quirk); in intel_set_dpcd_quirk()
23 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
28 drm_info(display->drm, "applying lvds SSC disable quirk\n"); in quirk_ssc_force_disable()
38 drm_info(display->drm, "applying inverted panel brightness quirk\n"); in quirk_invert_brightness()
45 drm_info(display->drm, "applying backlight present quirk\n"); in quirk_backlight_present()
48 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
54 drm_info(display->drm, "Applying T12 delay quirk\n"); in quirk_increase_t12_delay()
64 drm_info(display->drm, "Applying Increase DDI Disabled quirk\n"); in quirk_increase_ddi_disabled_time()
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/linux/drivers/phy/st/
H A Dphy-miphy28lp.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
169 * On STiH407 the glue logic can be different among MiPHY devices; for example:
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 bool ssc; member
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
373 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
374 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
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H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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