1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
169  * On STiH407 the glue logic can be different among MiPHY devices; for example:
171  *  0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173  *  1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 	bool ssc;  member
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 	void __iomem *base = miphy_phy->base;  in miphy28lp_set_reset()
373 	/* Bringing the MIPHY-CPU registers out of reset */  in miphy28lp_set_reset()
374 	if (miphy_phy->type == PHY_TYPE_PCIE) {  in miphy28lp_set_reset()
386 	void __iomem *base = miphy_phy->base;  in miphy28lp_pll_calibration()
391 	writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);  in miphy28lp_pll_calibration()
394 	writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);  in miphy28lp_pll_calibration()
395 	writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);  in miphy28lp_pll_calibration()
396 	writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);  in miphy28lp_pll_calibration()
397 	writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);  in miphy28lp_pll_calibration()
398 	writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);  in miphy28lp_pll_calibration()
407 	if (miphy_phy->type != PHY_TYPE_SATA)  in miphy28lp_pll_calibration()
412 	if (miphy_phy->type == PHY_TYPE_USB3) {  in miphy28lp_pll_calibration()
427 	void __iomem *base = miphy_phy->base;  in miphy28lp_sata_config_gen()
434 		writeb_relaxed(gen->bank, base + MIPHY_CONF);  in miphy28lp_sata_config_gen()
435 		writeb_relaxed(gen->speed, base + MIPHY_SPEED);  in miphy28lp_sata_config_gen()
436 		writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);  in miphy28lp_sata_config_gen()
437 		writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);  in miphy28lp_sata_config_gen()
440 		writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);  in miphy28lp_sata_config_gen()
441 		writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);  in miphy28lp_sata_config_gen()
444 		writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);  in miphy28lp_sata_config_gen()
445 		writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);  in miphy28lp_sata_config_gen()
446 		writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);  in miphy28lp_sata_config_gen()
447 		writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);  in miphy28lp_sata_config_gen()
448 		writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);  in miphy28lp_sata_config_gen()
454 	void __iomem *base = miphy_phy->base;  in miphy28lp_pcie_config_gen()
461 		writeb_relaxed(gen->bank, base + MIPHY_CONF);  in miphy28lp_pcie_config_gen()
462 		writeb_relaxed(gen->speed, base + MIPHY_SPEED);  in miphy28lp_pcie_config_gen()
463 		writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);  in miphy28lp_pcie_config_gen()
464 		writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);  in miphy28lp_pcie_config_gen()
467 		writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);  in miphy28lp_pcie_config_gen()
468 		writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);  in miphy28lp_pcie_config_gen()
469 		writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);  in miphy28lp_pcie_config_gen()
471 		writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);  in miphy28lp_pcie_config_gen()
474 		writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);  in miphy28lp_pcie_config_gen()
475 		writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);  in miphy28lp_pcie_config_gen()
476 		writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);  in miphy28lp_pcie_config_gen()
477 		writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);  in miphy28lp_pcie_config_gen()
486 	return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6,  in miphy28lp_wait_compensation()
494 	void __iomem *base = miphy_phy->base;  in miphy28lp_compensation()
501 	writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);  in miphy28lp_compensation()
504 	if (miphy_phy->type == PHY_TYPE_PCIE)  in miphy28lp_compensation()
511 	/* TX compensation offset to re-center TX impedance */  in miphy28lp_compensation()
514 	if (miphy_phy->type == PHY_TYPE_PCIE)  in miphy28lp_compensation()
522 	void __iomem *base = miphy_phy->base;  in miphy28_usb3_miphy_reset()
550 	void __iomem *base = miphy_phy->base;  in miphy_sata_tune_ssc()
555 	 * Enable the SSC on PLL for all banks  in miphy_sata_tune_ssc()
556 	 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp  in miphy_sata_tune_ssc()
570 		/* and define the period length of the SSC */  in miphy_sata_tune_ssc()
588 	void __iomem *base = miphy_phy->base;  in miphy_pcie_tune_ssc()
593 	 * Enable the SSC on PLL for all banks  in miphy_pcie_tune_ssc()
594 	 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp  in miphy_pcie_tune_ssc()
629 	writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);  in miphy_tune_tx_impedance()
634 	void __iomem *base = miphy_phy->base;  in miphy28lp_configure_sata()
660 	if (miphy_phy->px_rx_pol_inv) {  in miphy28lp_configure_sata()
662 		val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);  in miphy28lp_configure_sata()
664 		writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);  in miphy28lp_configure_sata()
667 	if (miphy_phy->ssc)  in miphy28lp_configure_sata()
670 	if (miphy_phy->tx_impedance)  in miphy28lp_configure_sata()
678 	void __iomem *base = miphy_phy->base;  in miphy28lp_configure_pcie()
703 	if (miphy_phy->ssc)  in miphy28lp_configure_pcie()
706 	if (miphy_phy->tx_impedance)  in miphy28lp_configure_pcie()
715 	void __iomem *base = miphy_phy->base;  in miphy28lp_configure_usb3()
746 	/* TX compensation offset to re-center TX impedance */  in miphy28lp_configure_usb3()
749 	/* Enable GENSEL_SEL and SSC */  in miphy28lp_configure_usb3()
758 	/* SSC modulation */  in miphy28lp_configure_usb3()
803 	if (miphy_phy->type == PHY_TYPE_SATA)  in miphy_is_ready()
806 	return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1,  in miphy_is_ready()
813 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy_osc_is_ready()
816 	if (!miphy_phy->osc_rdy)  in miphy_osc_is_ready()
819 	if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])  in miphy_osc_is_ready()
820 		return -EINVAL;  in miphy_osc_is_ready()
822 	return regmap_read_poll_timeout(miphy_dev->regmap,  in miphy_osc_is_ready()
823 					miphy_phy->syscfg_reg[SYSCFG_STATUS],  in miphy_osc_is_ready()
833 	index = of_property_match_string(child, "reg-names", rname);  in miphy28lp_get_resource_byname()
835 		return -ENODEV;  in miphy28lp_get_resource_byname()
853 			return -ENOENT;  in miphy28lp_get_one_addr()
864 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_setup()
866 	if (!miphy_phy->syscfg_reg[SYSCFG_CTRL])  in miphy28lp_setup()
867 		return -EINVAL;  in miphy28lp_setup()
869 	err = reset_control_assert(miphy_phy->miphy_rst);  in miphy28lp_setup()
871 		dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");  in miphy28lp_setup()
875 	if (miphy_phy->osc_force_ext)  in miphy28lp_setup()
878 	regmap_update_bits(miphy_dev->regmap,  in miphy28lp_setup()
879 			   miphy_phy->syscfg_reg[SYSCFG_CTRL],  in miphy28lp_setup()
882 	err = reset_control_deassert(miphy_phy->miphy_rst);  in miphy28lp_setup()
884 		dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");  in miphy28lp_setup()
893 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init_sata()
896 	if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||  in miphy28lp_init_sata()
897 			(!miphy_phy->syscfg_reg[SYSCFG_PCI]) ||  in miphy28lp_init_sata()
898 			(!miphy_phy->base))  in miphy28lp_init_sata()
899 		return -EINVAL;  in miphy28lp_init_sata()
901 	dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);  in miphy28lp_init_sata()
903 	/* Configure the glue-logic */  in miphy28lp_init_sata()
904 	sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);  in miphy28lp_init_sata()
906 	regmap_update_bits(miphy_dev->regmap,  in miphy28lp_init_sata()
907 			   miphy_phy->syscfg_reg[SYSCFG_SATA],  in miphy28lp_init_sata()
910 	regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],  in miphy28lp_init_sata()
917 		dev_err(miphy_dev->dev, "SATA phy setup failed\n");  in miphy28lp_init_sata()
929 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init_pcie()
932 	if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||  in miphy28lp_init_pcie()
933 			(!miphy_phy->syscfg_reg[SYSCFG_PCI])  in miphy28lp_init_pcie()
934 		|| (!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_pcie()
935 		return -EINVAL;  in miphy28lp_init_pcie()
937 	dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);  in miphy28lp_init_pcie()
939 	/* Configure the glue-logic */  in miphy28lp_init_pcie()
940 	regmap_update_bits(miphy_dev->regmap,  in miphy28lp_init_pcie()
941 			   miphy_phy->syscfg_reg[SYSCFG_SATA],  in miphy28lp_init_pcie()
944 	regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],  in miphy28lp_init_pcie()
951 		dev_err(miphy_dev->dev, "PCIe phy setup failed\n");  in miphy28lp_init_pcie()
961 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */  in miphy28lp_init_pcie()
962 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */  in miphy28lp_init_pcie()
963 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */  in miphy28lp_init_pcie()
964 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */  in miphy28lp_init_pcie()
965 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */  in miphy28lp_init_pcie()
966 	writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */  in miphy28lp_init_pcie()
974 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init_usb3()
977 	if ((!miphy_phy->base) || (!miphy_phy->pipebase))  in miphy28lp_init_usb3()
978 		return -EINVAL;  in miphy28lp_init_usb3()
980 	dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);  in miphy28lp_init_usb3()
985 		dev_err(miphy_dev->dev, "USB3 phy setup failed\n");  in miphy28lp_init_usb3()
993 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);  in miphy28lp_init_usb3()
994 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);  in miphy28lp_init_usb3()
995 	writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);  in miphy28lp_init_usb3()
996 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);  in miphy28lp_init_usb3()
997 	writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);  in miphy28lp_init_usb3()
998 	writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);  in miphy28lp_init_usb3()
1000 	/* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */  in miphy28lp_init_usb3()
1001 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);  in miphy28lp_init_usb3()
1002 	writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);  in miphy28lp_init_usb3()
1003 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);  in miphy28lp_init_usb3()
1004 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);  in miphy28lp_init_usb3()
1005 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);  in miphy28lp_init_usb3()
1006 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);  in miphy28lp_init_usb3()
1007 	writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);  in miphy28lp_init_usb3()
1008 	writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);  in miphy28lp_init_usb3()
1016 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_init()
1019 	mutex_lock(&miphy_dev->miphy_mutex);  in miphy28lp_init()
1021 	switch (miphy_phy->type) {  in miphy28lp_init()
1033 		ret = -EINVAL;  in miphy28lp_init()
1037 	mutex_unlock(&miphy_dev->miphy_mutex);  in miphy28lp_init()
1044 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_get_addr()
1045 	struct device_node *phynode = miphy_phy->phy->dev.of_node;  in miphy28lp_get_addr()
1048 	if ((miphy_phy->type != PHY_TYPE_SATA) &&  in miphy28lp_get_addr()
1049 	    (miphy_phy->type != PHY_TYPE_PCIE) &&  in miphy28lp_get_addr()
1050 	    (miphy_phy->type != PHY_TYPE_USB3)) {  in miphy28lp_get_addr()
1051 		return -EINVAL;  in miphy28lp_get_addr()
1054 	err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,  in miphy28lp_get_addr()
1055 			PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],  in miphy28lp_get_addr()
1056 			&miphy_phy->base);  in miphy28lp_get_addr()
1060 	if ((miphy_phy->type == PHY_TYPE_PCIE) ||  in miphy28lp_get_addr()
1061 	    (miphy_phy->type == PHY_TYPE_USB3)) {  in miphy28lp_get_addr()
1062 		err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",  in miphy28lp_get_addr()
1063 					     &miphy_phy->pipebase);  in miphy28lp_get_addr()
1076 	struct device_node *phynode = args->np;  in miphy28lp_xlate()
1079 	if (args->args_count != 1) {  in miphy28lp_xlate()
1081 		return ERR_PTR(-EINVAL);  in miphy28lp_xlate()
1084 	for (index = 0; index < miphy_dev->nphys; index++)  in miphy28lp_xlate()
1085 		if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {  in miphy28lp_xlate()
1086 			miphy_phy = miphy_dev->phys[index];  in miphy28lp_xlate()
1092 		return ERR_PTR(-EINVAL);  in miphy28lp_xlate()
1095 	miphy_phy->type = args->args[0];  in miphy28lp_xlate()
1101 	return miphy_phy->phy;  in miphy28lp_xlate()
1112 	struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;  in miphy28lp_probe_resets()
1115 	miphy_phy->miphy_rst =  in miphy28lp_probe_resets()
1116 		of_reset_control_get_shared(node, "miphy-sw-rst");  in miphy28lp_probe_resets()
1118 	if (IS_ERR(miphy_phy->miphy_rst)) {  in miphy28lp_probe_resets()
1119 		dev_err(miphy_dev->dev,  in miphy28lp_probe_resets()
1121 		return PTR_ERR(miphy_phy->miphy_rst);  in miphy28lp_probe_resets()
1124 	err = reset_control_deassert(miphy_phy->miphy_rst);  in miphy28lp_probe_resets()
1126 		dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");  in miphy28lp_probe_resets()
1139 	miphy_phy->osc_force_ext =  in miphy28lp_of_probe()
1140 		of_property_read_bool(np, "st,osc-force-ext");  in miphy28lp_of_probe()
1142 	miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");  in miphy28lp_of_probe()
1144 	miphy_phy->px_rx_pol_inv =  in miphy28lp_of_probe()
1147 	miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");  in miphy28lp_of_probe()
1149 	miphy_phy->tx_impedance =  in miphy28lp_of_probe()
1150 		of_property_read_bool(np, "st,tx-impedance-comp");  in miphy28lp_of_probe()
1152 	of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);  in miphy28lp_of_probe()
1153 	if (!miphy_phy->sata_gen)  in miphy28lp_of_probe()
1154 		miphy_phy->sata_gen = SATA_GEN1;  in miphy28lp_of_probe()
1158 			miphy_phy->syscfg_reg[i] = ctrlreg;  in miphy28lp_of_probe()
1166 	struct device_node *child, *np = pdev->dev.of_node;  in miphy28lp_probe()
1172 	miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);  in miphy28lp_probe()
1174 		return -ENOMEM;  in miphy28lp_probe()
1176 	miphy_dev->nphys = of_get_child_count(np);  in miphy28lp_probe()
1177 	miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,  in miphy28lp_probe()
1178 				       sizeof(*miphy_dev->phys), GFP_KERNEL);  in miphy28lp_probe()
1179 	if (!miphy_dev->phys)  in miphy28lp_probe()
1180 		return -ENOMEM;  in miphy28lp_probe()
1182 	miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");  in miphy28lp_probe()
1183 	if (IS_ERR(miphy_dev->regmap)) {  in miphy28lp_probe()
1184 		dev_err(miphy_dev->dev, "No syscfg phandle specified\n");  in miphy28lp_probe()
1185 		return PTR_ERR(miphy_dev->regmap);  in miphy28lp_probe()
1188 	miphy_dev->dev = &pdev->dev;  in miphy28lp_probe()
1190 	dev_set_drvdata(&pdev->dev, miphy_dev);  in miphy28lp_probe()
1192 	mutex_init(&miphy_dev->miphy_mutex);  in miphy28lp_probe()
1197 		miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),  in miphy28lp_probe()
1200 			ret = -ENOMEM;  in miphy28lp_probe()
1204 		miphy_dev->phys[port] = miphy_phy;  in miphy28lp_probe()
1206 		phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops);  in miphy28lp_probe()
1208 			dev_err(&pdev->dev, "failed to create PHY\n");  in miphy28lp_probe()
1213 		miphy_dev->phys[port]->phy = phy;  in miphy28lp_probe()
1214 		miphy_dev->phys[port]->phydev = miphy_dev;  in miphy28lp_probe()
1220 		ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);  in miphy28lp_probe()
1224 		phy_set_drvdata(phy, miphy_dev->phys[port]);  in miphy28lp_probe()
1229 	provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);  in miphy28lp_probe()
1237 	{.compatible = "st,miphy28lp-phy", },
1246 		.name = "miphy28lp-phy",