1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 26c742509SSedji Gaouaou /* 36c742509SSedji Gaouaou * atmel_ssc_dai.h - ALSA SSC interface for the Atmel SoC 46c742509SSedji Gaouaou * 56c742509SSedji Gaouaou * Copyright (C) 2005 SAN People 66c742509SSedji Gaouaou * Copyright (C) 2008 Atmel 76c742509SSedji Gaouaou * 86c742509SSedji Gaouaou * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> 96c742509SSedji Gaouaou * ATMEL CORP. 106c742509SSedji Gaouaou * 116c742509SSedji Gaouaou * Based on at91-ssc.c by 126c742509SSedji Gaouaou * Frank Mandarino <fmandarino@endrelia.com> 136c742509SSedji Gaouaou * Based on pxa2xx Platform drivers by 1464ca0404SLiam Girdwood * Liam Girdwood <lrg@slimlogic.co.uk> 156c742509SSedji Gaouaou */ 166c742509SSedji Gaouaou 176c742509SSedji Gaouaou #ifndef _ATMEL_SSC_DAI_H 186c742509SSedji Gaouaou #define _ATMEL_SSC_DAI_H 196c742509SSedji Gaouaou 206c742509SSedji Gaouaou #include <linux/types.h> 216c742509SSedji Gaouaou #include <linux/atmel-ssc.h> 226c742509SSedji Gaouaou 236c742509SSedji Gaouaou #include "atmel-pcm.h" 246c742509SSedji Gaouaou 256c742509SSedji Gaouaou /* SSC system clock ids */ 266c742509SSedji Gaouaou #define ATMEL_SYSCLK_MCK 0 /* SSC uses AT91 MCK as system clock */ 276c742509SSedji Gaouaou 286c742509SSedji Gaouaou /* SSC divider ids */ 296c742509SSedji Gaouaou #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */ 306c742509SSedji Gaouaou #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */ 316c742509SSedji Gaouaou #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */ 326c742509SSedji Gaouaou /* 336c742509SSedji Gaouaou * SSC direction masks 346c742509SSedji Gaouaou */ 356c742509SSedji Gaouaou #define SSC_DIR_MASK_UNUSED 0 366c742509SSedji Gaouaou #define SSC_DIR_MASK_PLAYBACK 1 376c742509SSedji Gaouaou #define SSC_DIR_MASK_CAPTURE 2 386c742509SSedji Gaouaou 396c742509SSedji Gaouaou /* 406c742509SSedji Gaouaou * SSC register values that Atmel left out of <linux/atmel-ssc.h>. These 416c742509SSedji Gaouaou * are expected to be used with SSC_BF 426c742509SSedji Gaouaou */ 436c742509SSedji Gaouaou /* START bit field values */ 446c742509SSedji Gaouaou #define SSC_START_CONTINUOUS 0 456c742509SSedji Gaouaou #define SSC_START_TX_RX 1 466c742509SSedji Gaouaou #define SSC_START_LOW_RF 2 476c742509SSedji Gaouaou #define SSC_START_HIGH_RF 3 486c742509SSedji Gaouaou #define SSC_START_FALLING_RF 4 496c742509SSedji Gaouaou #define SSC_START_RISING_RF 5 506c742509SSedji Gaouaou #define SSC_START_LEVEL_RF 6 516c742509SSedji Gaouaou #define SSC_START_EDGE_RF 7 526c742509SSedji Gaouaou #define SSS_START_COMPARE_0 8 536c742509SSedji Gaouaou 546c742509SSedji Gaouaou /* CKI bit field values */ 556c742509SSedji Gaouaou #define SSC_CKI_FALLING 0 566c742509SSedji Gaouaou #define SSC_CKI_RISING 1 576c742509SSedji Gaouaou 586c742509SSedji Gaouaou /* CKO bit field values */ 596c742509SSedji Gaouaou #define SSC_CKO_NONE 0 606c742509SSedji Gaouaou #define SSC_CKO_CONTINUOUS 1 616c742509SSedji Gaouaou #define SSC_CKO_TRANSFER 2 626c742509SSedji Gaouaou 636c742509SSedji Gaouaou /* CKS bit field values */ 646c742509SSedji Gaouaou #define SSC_CKS_DIV 0 656c742509SSedji Gaouaou #define SSC_CKS_CLOCK 1 666c742509SSedji Gaouaou #define SSC_CKS_PIN 2 676c742509SSedji Gaouaou 686c742509SSedji Gaouaou /* FSEDGE bit field values */ 696c742509SSedji Gaouaou #define SSC_FSEDGE_POSITIVE 0 706c742509SSedji Gaouaou #define SSC_FSEDGE_NEGATIVE 1 716c742509SSedji Gaouaou 726c742509SSedji Gaouaou /* FSOS bit field values */ 736c742509SSedji Gaouaou #define SSC_FSOS_NONE 0 746c742509SSedji Gaouaou #define SSC_FSOS_NEGATIVE 1 756c742509SSedji Gaouaou #define SSC_FSOS_POSITIVE 2 766c742509SSedji Gaouaou #define SSC_FSOS_LOW 3 776c742509SSedji Gaouaou #define SSC_FSOS_HIGH 4 786c742509SSedji Gaouaou #define SSC_FSOS_TOGGLE 5 796c742509SSedji Gaouaou 806c742509SSedji Gaouaou #define START_DELAY 1 816c742509SSedji Gaouaou 826c742509SSedji Gaouaou struct atmel_ssc_state { 836c742509SSedji Gaouaou u32 ssc_cmr; 846c742509SSedji Gaouaou u32 ssc_rcmr; 856c742509SSedji Gaouaou u32 ssc_rfmr; 866c742509SSedji Gaouaou u32 ssc_tcmr; 876c742509SSedji Gaouaou u32 ssc_tfmr; 886c742509SSedji Gaouaou u32 ssc_sr; 896c742509SSedji Gaouaou u32 ssc_imr; 906c742509SSedji Gaouaou }; 916c742509SSedji Gaouaou 926c742509SSedji Gaouaou 936c742509SSedji Gaouaou struct atmel_ssc_info { 946c742509SSedji Gaouaou char *name; 956c742509SSedji Gaouaou struct ssc_device *ssc; 966c742509SSedji Gaouaou unsigned short dir_mask; /* 0=unused, 1=playback, 2=capture */ 976c742509SSedji Gaouaou unsigned short initialized; /* true if SSC has been initialized */ 986c742509SSedji Gaouaou unsigned short daifmt; 996c742509SSedji Gaouaou unsigned short cmr_div; 1006c742509SSedji Gaouaou unsigned short tcmr_period; 1016c742509SSedji Gaouaou unsigned short rcmr_period; 102a85787edSPeter Rosin unsigned int forced_divider; 1036c742509SSedji Gaouaou struct atmel_pcm_dma_params *dma_params[2]; 1046c742509SSedji Gaouaou struct atmel_ssc_state ssc_state; 105b6d6c6e9SPeter Rosin unsigned long mck_rate; 1066c742509SSedji Gaouaou }; 1076c742509SSedji Gaouaou 108be681a82SBo Shen int atmel_ssc_set_audio(int ssc_id); 109be681a82SBo Shen void atmel_ssc_put_audio(int ssc_id); 110abfa4eaeSMark Brown 1116c742509SSedji Gaouaou #endif /* _AT91_SSC_DAI_H */ 112