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/linux/drivers/mtd/devices/
H A Dsst25l.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Driver for SST25L SPI Flash chips
24 #include <linux/spi/spi.h>
25 #include <linux/spi/flash.h>
47 struct spi_device *spi; member
67 static int sst25l_status(struct sst25l_flash *flash, int *status) in sst25l_status() argument
83 err = spi_sync(flash->spi, &m); in sst25l_status()
91 static int sst25l_write_enable(struct sst25l_flash *flash, int enable) in sst25l_write_enable() argument
97 err = spi_write(flash->spi, command, 1); in sst25l_write_enable()
102 err = spi_write(flash->spi, command, 1); in sst25l_write_enable()
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H A Dmchp23k256.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Driver for Microchip 23k256 SPI RAM chips
16 #include <linux/spi/flash.h>
17 #include <linux/spi/spi.h>
28 struct spi_device *spi; member
41 static void mchp23k256_addr2cmd(struct mchp23k256_flash *flash, in mchp23k256_addr2cmd() argument
51 for (i = flash->caps->addr_width; i > 0; i--, addr >>= 8) in mchp23k256_addr2cmd()
55 static int mchp23k256_cmdsz(struct mchp23k256_flash *flash) in mchp23k256_cmdsz() argument
57 return 1 + flash->caps->addr_width; in mchp23k256_cmdsz()
63 struct mchp23k256_flash *flash = to_mchp23k256_flash(mtd); in mchp23k256_write() local
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Self-contained MTD device drivers"
12 These devices come in memory configurations from 32M - 1G. If you
41 tristate "DEC MS02-NV NVRAM module support"
44 This is an MTD driver for the DEC's MS02-NV (54-20948-01) battery
45 backed-up NVRAM module. The module was originally meant as an NFS
52 The module will be called ms02-nv.
58 This enables access to AT45xxx DataFlash chips, using SPI.
59 Sometimes DataFlash chips are packaged inside MMC-format
66 This adds an extra check when data is written to the flash.
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H A Dmtd_dataflash.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework
6 * Copyright (C) 2003-2005 SAN People (Pty) Ltd
17 #include <linux/spi/spi.h>
18 #include <linux/spi/flash.h>
24 * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
28 * Sometimes DataFlash is packaged in MMC-format cards, although the
46 /* erasing flash */
50 /* move data between buffer and flash */
57 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
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/linux/Documentation/driver-api/mtd/
H A Dspi-nor.rst2 SPI NOR framework
5 How to propose a new flash addition
6 -----------------------------------
8 Most SPI NOR flashes comply with the JEDEC JESD216
9 Serial Flash Discoverable Parameter (SFDP) standard. SFDP describes
10 the functional and feature capabilities of serial flash devices in a
11 standard set of internal read-only parameter tables.
13 The SPI NOR driver queries the SFDP tables in order to determine the
14 flash's parameters and settings. If the flash defines the SFDP tables
15 it's likely that you won't need a flash entry at all, and instead
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H A Dspi-intel.rst2 Upgrading BIOS using spi-intel
5 Many Intel CPUs like Baytrail and Braswell include SPI serial flash host
7 Since contents of the SPI serial flash is crucial for machine to function,
11 Not all manufacturers protect the SPI serial flash, mainly because it
14 The spi-intel driver makes it possible to read and write the SPI serial
15 flash, if certain protection bits are not set and locked. If it finds
16 any of them set, the whole MTD device is made read-only to prevent
17 partial overwrites. By default the driver exposes SPI serial flash
18 contents as read-only but it can be changed from kernel command line,
21 Please keep in mind that overwriting the BIOS image on SPI serial flash
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-spi-devices-spi-nor1 What: /sys/bus/spi/devices/.../spi-nor/jedec_id
4 Contact: linux-mtd@lists.infradead.org
5 Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the
6 flash device.
8 The attribute is not present if the flash doesn't support
10 non-JEDEC compliant flashes.
12 What: /sys/bus/spi/devices/.../spi-nor/manufacturer
15 Contact: linux-mtd@lists.infradead.org
16 Description: (RO) Manufacturer of the SPI NOR flash.
18 The attribute is not present if the flash device isn't
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/linux/Documentation/devicetree/bindings/mtd/
H A Dnxp-spifi.txt1 * NXP SPI Flash Interface (SPIFI)
3 NXP SPIFI is a specialized SPI interface for serial Flash devices.
4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
6 mode. In memory mode the Flash is accessible from the CPU as
10 - compatible : Should be "nxp,lpc1773-spifi"
11 - reg : the first contains the register location and length,
13 - reg-names: Should contain the reg names "spifi" and "flash"
14 - interrupts : Should contain the interrupt for the device
15 - clocks : The clocks needed by the SPIFI controller
16 - clock-names : Should contain the clock names "spifi" and "reg"
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H A Dhisilicon,fmc-spi-nor.txt1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
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H A Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
17 pattern: "^(flash|.*sram|nand)(@.*)?$"
21 User-defined MTD device name. Can be used to assign user friendly
22 names to MTD devices (instead of the flash model or flash controller
23 based name) in order to ease flash device identification and/or
26 '#address-cells':
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/linux/drivers/mtd/spi-nor/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SPI NOR device support"
8 This is the framework for the SPI NOR which can be used by the SPI
9 device drivers and the SPI NOR device driver.
17 Many flash memories support erasing small (4096 B) sectors. Depending
20 Changing a small part of the flash's contents is usually faster with
34 This option disables the software write protection on any SPI
35 flashes at boot-up.
37 Depending on the flash chip this either clears the block protection
41 of your SPI flash. This is only to keep backwards compatibility.
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
24 #include <linux/spi/flash.h>
31 * For everything but full-chip erase; probably could be much smaller, but kept
37 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
38 * for larger flash
48 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
61 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
63 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
66 return op->cmd.opcode; in spi_nor_get_cmd_ext()
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
24 flash@0 {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
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H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
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H A Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
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/linux/Documentation/devicetree/bindings/spi/
H A Damlogic,meson6-spifc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SPI Flash Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: spi-controller.yaml#
17 The Meson SPIFC is a controller optimized for communication with SPI
18 NOR memories, without DMA support and a 64-byte unified transmit /
24 - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
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H A Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
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H A Dmediatek,spi-mtk-snfi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
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H A Daspeed,ast2600-fmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
11 - Cédric Le Goater <clg@kaod.org>
15 SPI) of the AST2400, AST2500 and AST2600 SOCs.
18 - $ref: spi-controller.yaml#
23 - aspeed,ast2600-fmc
24 - aspeed,ast2600-spi
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H A Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
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/linux/drivers/mtd/spi-nor/controllers/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Hisilicon FMC SPI NOR Flash Controller(SFC)"
7 This enables support for HiSilicon FMC SPI NOR flash controller.
10 tristate "NXP SPI Flash Interface (SPIFI)"
14 Enable support for the NXP LPC SPI Flash Interface controller.
16 SPIFI is a specialized controller for connecting serial SPI
17 Flash. Enable this option if you have a device with a SPIFI
18 controller and want to access the Flash as a mtd device.
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drenesas,rpc-if.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
17 The flash interface is selected based on the "compatible" property of this
19 - if it contains "jedec,spi-nor", then SPI is used;
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/linux/arch/powerpc/boot/dts/fsl/
H A Dp1010rdb.dtsi2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
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/linux/drivers/firmware/microchip/
H A Dmpfs-auto-update.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (c) 2022-2023 Microchip Corporation. All rights reserved.
43 * SPI Flash layout example:
44 * |------------------------------| 0x0000000
46 * | SPI "directories" |
47 * |------------------------------| 0x0000400
51 * |------------------------------| 0x0100400
54 * |------------------------------| 0x1500400
57 * |------------------------------| 0x2900400
59 * | Reserved for multi-image IAP |
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/linux/include/linux/mtd/
H A Dspi-nor.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <linux/spi/spi-mem.h>
18 * requires a 4-byte (32-bit) address.
21 /* Flash opcodes. */
30 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
31 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
34 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
35 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
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