Lines Matching +full:spi +full:- +full:flash

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Biju Das <biju.das.jz@bp.renesas.com>
13   Renesas xSPI allows a SPI flash connected to the SoC to be accessed via
14   the memory-mapping or the manual command mode.
16   The flash chip itself should be represented by a subnode of the XSPI node.
17   The flash interface is selected based on the "compatible" property of this
19   -  "jedec,spi-nor";
22   - $ref: /schemas/spi/spi-controller.yaml#
26     const: renesas,r9a09g047-xspi  # RZ/G3E
30       - description: xSPI registers
31       - description: direct mapping area
33   reg-names:
35       - const: regs
36       - const: dirmap
40       - description: Interrupt pulse signal by factors excluding errors
41       - description: Interrupt pulse signal by error factors
43   interrupt-names:
45       - const: pulse
46       - const: err_pulse
50       - description: AHB clock
51       - description: AXI clock
52       - description: SPI clock
53       - description: Double speed SPI clock
55   clock-names:
57       - const: ahb
58       - const: axi
59       - const: spi
60       - const: spix2
62   power-domains:
67       - description: Hardware reset
68       - description: AXI reset
70   reset-names:
72       - const: hresetn
73       - const: aresetn
75   renesas,xspi-cs-addr-sys:
82   "flash@[0-9a-f]+$":
89           const: jedec,spi-nor
92   - compatible
93   - reg
94   - reg-names
95   - interrupts
96   - interrupt-names
97   - clocks
98   - clock-names
99   - power-domains
100   - resets
101   - reset-names
102   - '#address-cells'
103   - '#size-cells'
108   - |
109     #include <dt-bindings/interrupt-controller/arm-gic.h>
110     #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
112     spi@11030000 {
113         compatible = "renesas,r9a09g047-xspi";
115         reg-names = "regs", "dirmap";
118         interrupt-names = "pulse", "err_pulse";
121         clock-names = "ahb", "axi", "spi", "spix2";
122         power-domains = <&cpg>;
124         reset-names = "hresetn", "aresetn";
125         #address-cells = <1>;
126         #size-cells = <0>;
128         flash@0 {
129           compatible = "jedec,spi-nor";
131           spi-max-frequency = <40000000>;
132           spi-tx-bus-width = <1>;
133           spi-rx-bus-width = <1>;