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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
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H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
21 Requirements to SPI slave nodes:
23 - There can be only one slave device.
[all …]
H A Drenesas,sh-msiof.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas MSIOF SPI / I2S controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
17 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
19 - items:
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/linux/Documentation/devicetree/bindings/rtc/
H A Dnxp,pcf85063.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - microcrystal,rv8063
16 - microcrystal,rv8263
17 - nxp,pcf85063
18 - nxp,pcf85063a
19 - nxp,pcf85063tp
20 - nxp,pca85073a
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H A Depson,rx6110.txt4 The Epson RX6110 can be used with SPI or I2C busses. The kind of
8 --------
11 - compatible: should be: "epson,rx6110"
12 - reg : the I2C address of the device for I2C
21 SPI mode
22 --------
25 - compatible: should be: "epson,rx6110"
26 - reg: chip select number
27 - spi-cs-high: RX6110 needs chipselect high
28 - spi-cpha: RX6110 works with SPI shifted clock phase
[all …]
H A Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
12 - compatible : Should be "maxim,ds1302"
14 Required SPI properties:
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
27 - spi-cs-high: DS-1302 has active high chip select line. This is
32 spi@901c {
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD)
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
22 wakeup-source;
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dnxp,mc33xs2410.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-side switch MC33XS2410
10 - Dimitri Fedrau <dima.fedrau@gmail.com>
13 - $ref: pwm.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 spi-max-frequency:
26 spi-cpha: true
28 spi-cs-setup-delay-ns:
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/linux/drivers/spi/
H A Dspi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI host driver using generic bitbanged GPIO
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
17 #include <linux/spi/spi_gpio.h>
20 * This bitbanging SPI host driver should help make systems usable
21 * when a native hardware SPI engine is not available, perhaps because
25 * platform_device->driver_data ... points to spi_gpio
27 * spi->controller_state ... reserved for bitbang framework code
29 * spi->controller->dev.driver_data ... points to spi_gpio->bitbang
[all …]
H A Dspi-ppc4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI_PPC4XX SPI controller driver.
9 * Based in part on drivers/spi/spi_s3c24xx.c
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18 * generate an interrupt to the CPU. This can cause high CPU utilization.
20 * during SPI transfers by setting max_speed_hz via the device tree.
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
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H A Dspi-bcmbca-hsspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCMBCA High Speed SPI Controller driver
5 * Copyright 2000-2010 Broadcom Corporation
6 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright 2019-2022 Broadcom Ltd
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
23 #include <linux/spi/spi-mem.h>
99 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
132 return sprintf(buf, "%d\n", bs->wait_mode); in wait_mode_show()
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H A Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Polling/bitbanging SPI host controller controller driver utilities
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi_bitbang.h>
22 /*----------------------------------------------------------------------*/
25 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
26 * Use this for GPIO or shift-register level hardware APIs.
28 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
30 * used, though maybe they're called from controller-aware code.
32 * chipselect() and friends may use spi_device->controller_data and
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H A Dspi-bcm63xx-hsspi.c2 * Broadcom BCM63XX High Speed SPI Controller driver
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
23 #include <linux/spi/spi-mem.h>
24 #include <linux/mtd/spi-nor.h>
105 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
114 * mode. If not, falls back to use the dummy cs workaround mode but limit the
124 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) \
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H A Dspi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Addy Ke <addy.ke@rock-chips.com>
14 #include <linux/spi/spi.h>
18 #define DRIVER_NAME "rockchip-spi"
25 /* SPI register offsets */
62 /* ss_n be high for half sclk_out cycles */
64 /* ss_n be high for one sclk_out cycle */
154 /* sclk_out: spi host internal logic in rk3x can support 50Mhz */
158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
195 bool cs_inactive; /* spi target transmission stop when cs inactive */
[all …]
H A Dspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // SPI init/core code
9 #include <linux/clk/clk-conf.h>
13 #include <linux/dma-mapping.h>
34 #include <linux/spi/offload/types.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi-mem.h>
40 #include <trace/events/spi.h>
50 struct spi_device *spi = to_spi_device(dev); in spidev_release() local
52 spi_controller_put(spi->controller); in spidev_release()
[all …]
/linux/drivers/iio/adc/
H A Dad7944.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/spi/offload/consumer.h>
20 #include <linux/spi/spi.h>
26 #include <linux/iio/buffer-dmaengine.h>
40 /* datasheet calls this "4-wire mode" */
42 /* datasheet calls this "3-wire mode" (not related to SPI_3WIRE!) */
48 /* maps adi,spi-mode property value to enum */
56 struct spi_device *spi; member
67 /* Chip-specific timing specifications. */
73 /* Indicates TURBO is hard-wired to be always enabled. */
[all …]
H A Dad4000.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AD4000 SPI ADC driver
18 #include <linux/spi/offload/consumer.h>
19 #include <linux/spi/spi.h>
25 #include <linux/iio/buffer-dmaengine.h>
36 #define AD4000_CFG_HIGHZ BIT(2) /* High impedance mode */
57 .shift = (_offl ? 0 : _storage_bits - _real_bits), \
68 * When SPI offload is configured, transfers are executed without CPU
95 .shift = (_offl ? 0 : _storage_bits - _real_bits), \
122 /* maps adi,sdi-pin property value to enum */
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST Microelectronics SPEAr SPI CS GPIO Controller
10 - Viresh Kumar <vireshk@kernel.org>
14 Cell spi controller through its system registers, which otherwise remains
17 desired by some of the device protocols above spi which expect (multiple)
27 const: st,spear-spics-gpio
32 gpio-controller: true
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dmotorola-cpcap.txt4 - compatible : One or both of "motorola,cpcap" or "ste,6556002"
5 - reg : SPI chip select
6 - interrupts : The interrupt line the device is connected to
7 - interrupt-controller : Marks the device node as an interrupt controller
8 - #interrupt-cells : The number of cells to describe an IRQ, should be 2
9 - #address-cells : Child device offset number of cells, should be 1
10 - #size-cells : Child device size number of cells, should be 0
11 - spi-max-frequency : Typically set to 3000000
12 - spi-cs-high : SPI chip select direction
16 The sub-functions of CPCAP get their own node with their own compatible values,
[all …]
/linux/include/linux/dma/
H A Dqcom-gpi-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum spi_transfer_cmd - spi transfer commands
19 * struct gpi_spi_config - spi config for peripheral
21 * @loopback_en: spi loopback enable when set
25 * @word_len: spi word length
28 * @cmd: spi cmd
29 * @fragmentation: keep CS asserted at end of sequence
30 * @cs: chip select toggle
42 u8 cs; member
55 * struct gpi_i2c_config - i2c config for peripheral
[all …]
/linux/arch/riscv/boot/dts/canaan/
H A Dsipeed_maix_bit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-bit", "sipeed,maix-bitm",
18 "canaan,kendryte-k210";
26 stdout-path = "serial0:115200n8";
29 gpio-leds {
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019-ap.dk07.1-c1.dts1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include "qcom-ipq4019-ap.dk07.1.dtsi"
8 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
9 compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";
14 perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
17 spi@78b6000 {
22 serial_1_pins: serial1-state {
26 bias-disable;
29 spi_0_pins: spi-0-state {
[all …]
H A Dqcom-ipq4019-ap.dk04.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
27 serial_0_pins: serial0-state {
30 bias-disable;
33 serial_1_pins: serial1-state {
37 bias-disable;
[all …]
/linux/drivers/gpio/
H A Dgpio-spear-spics.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPEAr platform SPI chipselect abstraction over gpiolib
21 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
22 * through system registers. This register lies outside spi (pl022)
25 * It provides control for spi chip select lines so that any chipselect
31 * struct spear_spics - represents spi chip select control
35 * @cs_value_bit: bit to program high or low chipselect
38 * @use_count: use count of a spi controller cs lines
61 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
62 if (spics->last_off != offset) { in spics_set_value()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]

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