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Searched +full:sp7021 +full:- +full:spi (Results 1 – 7 of 7) sorted by relevance

/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Sunplus SP7021
8 #include <dt-bindings/clock/sunplus,sp7021-clkc.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sunplus,sp7021-reset.h>
11 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
12 #include <dt-bindings/gpio/gpio.h>
17 compatible = "sunplus,sp7021";
18 model = "Sunplus SP7021";
22 compatible = "fixed-clock";
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sunplus-sp7021.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/spi-sunplus-sp7021.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus sp7021 SPI controller
11 - $ref: spi-controller.yaml
14 - Li-hao Kuo <lhjeff911@gmail.com>
19 - sunplus,sp7021-spi
23 - description: the SPI master registers
24 - description: the SPI slave registers
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsunplus,sp7021-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
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/linux/drivers/clk/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
55 depends on SPI
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
87 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
91 tristate "Raspberry Pi RP1-based clock support"
96 This multi-function device has 3 main PLLs and several clock
97 generators to drive the internal sub-peripherals.
106 multi-function device has one fixed-rate oscillator, clocked
137 be pre-programmed to support other configurations and features not yet
186 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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/linux/drivers/rtc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
141 once-per-second update interrupts, used for synchronization.
159 will be called rtc-test.
173 will be called rtc-88pm860x.
183 will be called rtc-88pm80x.
193 will be called rtc-88pm886.
197 tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3"
200 AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip.
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/drivers/pinctrl/sunplus/
H A Dsppctl_sp7021.c1 // SPDX-License-Identifier: GPL-2.0
3 * SP7021 Pin Controller Driver.
476 FNCN("SPIM0_INT", pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */
497 FNCN("SPI0S_INT", pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */