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/linux/arch/arm/mach-hisi/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
7 #include <linux/smp.h>
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
59 u32 offset = 0; in hi3xxx_smp_prepare_cpus() local
74 if (of_property_read_u32(np, "smp-offset", &offset) < 0) { in hi3xxx_smp_prepare_cpus()
76 pr_err("failed to find smp-offset property\n"); in hi3xxx_smp_prepare_cpus()
79 ctrl_base += offset; in hi3xxx_smp_prepare_cpus()
112 writel_relaxed(0xe51ff004, virt); /* ldr pc, [pc, #-4] */ in hix5hd2_set_scu_boot_addr()
[all …]
/linux/arch/powerpc/kernel/
H A Dsmp-tbsync.c1 // SPDX-License-Identifier: GPL-2.0
3 * Smp timebase synchronization for ppc.
11 #include <linux/smp.h>
15 #include <asm/smp.h>
42 tbsync->race_result = add; in enter_contest()
57 tbsync->ack = 1; in smp_generic_take_timebase()
58 while (!tbsync->handshake) in smp_generic_take_timebase()
62 cmd = tbsync->cmd; in smp_generic_take_timebase()
63 tb = tbsync->tb; in smp_generic_take_timebase()
65 tbsync->ack = 0; in smp_generic_take_timebase()
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/linux/drivers/scsi/isci/
H A Dscu_task_context.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
68 * enum scu_ssp_task_type - This enumberation defines the various SSP task
77 SCU_TASK_TYPE_SMP_REQUEST, /* /< SMP Request type */
84 * enum scu_sata_task_type - This enumeration defines the various SATA task
222 * MAKE_SCU_CONTEXT_COMMAND_TYPE() -
293 * struct ssp_task_context - This is the SCU hardware definition for an SSP
299 /* OFFSET 0x18 */
303 /* OFFSET 0x1C */
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/linux/arch/csky/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
41 select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
134 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
149 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
184 # VA_BITS - PAGE_SHIFT - 3
218 prompt "PAGE OFFSET"
222 bool "PAGE OFFSET 2G (user:kernel = 2:2)"
225 bool "PAGE OFFSET 2.5G (user:kernel = 2.5:1.5)"
234 prompt "C-SKY PMU type"
264 bool "Tightly-Coupled/Sram Memory"
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/linux/arch/arm/include/asm/
H A Dprocessor.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1995-1999 Russell King
20 #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
41 * Everything usercopied to/from thread_struct is statically-sized, so
44 static inline void arch_thread_struct_whitelist(unsigned long *offset, in arch_thread_struct_whitelist() argument
47 *offset = *size = 0; in arch_thread_struct_whitelist()
57 r7 = regs->ARM_r
93 __ALT_SMP_ASM(smp,up) global() argument
101 __ALT_SMP_ASM(smp,up) global() argument
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H A Dassembler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2000 Russell King
10 * Do not include any C declarations in this file - it is included by
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
26 #include <asm/uaccess-asm.h>
77 * set to write-allocate (this would need further testing on XScale when WA
128 stmdb sp!, {r0-r3, ip, lr}
132 ldmia sp!, {r0-r3, ip, lr}
144 stmdb sp!, {r0-r3, ip, lr}
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/linux/Documentation/devicetree/bindings/arm/cpu-enable-method/
H A Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
33 #address-cells = <1>;
34 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
19 offset. In addition, the HiP01 system controller has some specific control
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
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/linux/fs/jfs/
H A Djfs_dtree.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) International Business Machines Corp., 2000-2004
7 * jfs_dtree.c: directory B+-tree manager
9 * B+-tree with variable length key directory:
11 * each directory page is structured as an array of 32-byte
28 * directory starts as a root/leaf page in on-dis
242 s64 offset; find_index() local
333 s64 offset; add_index() local
931 struct metapage *smp; dtSplitUp() local
1330 struct metapage *smp; dtSplitPage() local
1643 struct metapage *smp, *pmp, *mp; dtExtendPage() local
1875 struct metapage *smp; dtSplitRoot() local
3139 dtReadNext(struct inode * ip,loff_t * offset,struct btstack * btstack) dtReadNext() argument
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/linux/drivers/gpio/
H A Dgpio-xtensa.c1 // SPDX-License-Identifier: GPL-2.0
22 * This driver is currently incompatible with SMP. The GPIO32 extension is not
24 * different set of IO wires. A theoretical SMP aware version of this driver
72 static int xtensa_impwire_get_direction(struct gpio_chip *gc, unsigned offset) in xtensa_impwire_get_direction() argument
77 static int xtensa_impwire_get_value(struct gpio_chip *gc, unsigned offset) in xtensa_impwire_get_value() argument
86 return !!(impwire & BIT(offset)); in xtensa_impwire_get_value()
89 static int xtensa_expstate_get_direction(struct gpio_chip *gc, unsigned offset) in xtensa_expstate_get_direction() argument
94 static int xtensa_expstate_get_value(struct gpio_chip *gc, unsigned offset) in xtensa_expstate_get_value() argument
103 return !!(expstate & BIT(offset)); in xtensa_expstate_get_value()
106 static int xtensa_expstate_set_value(struct gpio_chip *gc, unsigned int offset, in xtensa_expstate_set_value() argument
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/linux/arch/sh/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
80 <http://www.linux-sh.org/>.
94 depends on SMP && PREEMPTION
213 prompt "Processor sub-type selection"
219 # SH-2 Processor Support
230 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
232 # SH-2A Processor Support
278 bool "Support MX-G processor"
282 Select MX-G if running on an R8A03022BG part.
284 # SH-3 Processor Support
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/linux/kernel/irq/
H A Dipi.c1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
26 unsigned int nr_irqs, offset; in irq_reserve_ipi() local
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
54 offset = 0; in irq_reserve_ipi()
64 offset = cpumask_first(dest); in irq_reserve_ipi()
69 next = cpumask_next_zero(offset, dest); in irq_reserve_ipi()
74 return -EINVAL; in irq_reserve_ipi()
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/linux/arch/arm/mach-ux500/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009 ST-Ericsson.
14 #include <linux/smp.h>
36 np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram"); in ux500_smp_prepare_cpus()
48 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in ux500_smp_prepare_cpus()
71 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the in ux500_boot_secondary()
72 * backup ram register at offset 0x1FF0, which is what boot rom code in ux500_boot_secondary()
100 CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);
/linux/arch/mips/cavium-octeon/
H A Dsmp.c6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
10 #include <linux/smp.h>
23 #include <asm/smp.h>
104 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, in octeon_send_ipi_single()
131 if (labi->labi_signature != LABI_SIGNATURE) { in octeon_smp_hotplug_setup()
136 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; in octeon_smp_hotplug_setup()
164 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) { in octeon_smp_setup()
195 int plat_post_relocation(long offset) in plat_post_relocation() argument
200 octeon_processor_relocated_kernel_entry = entry + offset; in plat_post_relocation()
213 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, in octeon_boot_secondary()
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/linux/arch/loongarch/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
75 select ARCH_SUPPORTS_SCHED_SMT if SMP
76 select ARCH_SUPPORTS_SCHED_MC if SMP
256 # MIPS Loongson code, to preserve Loongson-specific code paths in drivers that
287 def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))
290 def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)
293 def_bool $(cc-option,-W
459 config SMP global() config
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/linux/arch/um/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "UML-specific options"
90 config SMP
91 bool "Symmetric multi-processing support"
95 This option enables UML SMP support.
104 runs within their respective single-threaded stubs.
106 That is, SMP support is available both within the kernel and
112 default 1 if !SMP
89 config SMP global() config
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/linux/arch/arm/mm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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/linux/arch/x86/kernel/
H A Dalternative.c1 // SPDX-License-Identifier: GPL-2.0-only
2 #define pr_fmt(fmt) "SMP alternatives: " fmt
10 #include <asm/text-patching.h>
12 #include <asm/insn-eval.h>
21 #define MAX_PATCH_LEN (255-1)
42 __setup("debug-alternative", debug_alt);
51 __setup("noreplace-sm in setup_noreplace_smp()
143 int offset = 0; its_init_thunk() local
353 skip_nops(u8 * buf,int offset,int len) skip_nops() argument
457 need_reloc(unsigned long offset,u8 * src,size_t src_len) need_reloc() argument
2118 struct smp_alt_module *smp; alternatives_smp_module_add() local
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/linux/arch/loongarch/kernel/
H A Dalternative.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #define MAX_PATCH_SIZE (((u8)(-1)) / LOONGARCH_INSN_SIZE)
23 __setup("debug-alternative", debug_alt);
41 for (_j = 0; _j < count - 1; _j++) \
50 while (count--) { in add_nops()
51 insn->word = INSN_NOP; in add_nops()
68 long offset; in recompute_jump() local
73 si_l = src->reg0i26_format.immediate_l; in recompute_jump()
74 si_h = src->reg0i26_format.immediate_h; in recompute_jump()
75 switch (src->reg0i26_format.opcode) { in recompute_jump()
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/linux/arch/arm/mach-tegra/
H A Dsleep.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
12 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
14 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
16 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
18 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
20 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
25 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
50 /* returns the offset of the flow controller halt register for a cpu */
59 /* returns the offset of the flow controller csr register for a cpu */
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/linux/arch/x86/include/asm/
H A Dalternative.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 * Alternative inline assembly for SMP.
29 * SMP alternatives use the same data structures as the other
31 * UP system running a SMP kernel. The existing apply_alternatives()
32 * works fine for patching a SMP kernel for UP.
34 * The SMP alternative tables can be kept after boot and contain both
35 * UP and SMP versions of the instructions to allow switching back to
36 * SMP at runtime, when hotplugging in a new CPU, which is especially
48 ".long 671f - .\n" /* offset */ \
70 s32 repl_offset; /* offset to replacement instruction */
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/linux/arch/parisc/include/asm/
H A Dalternative.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #define ALT_COND_NO_SMP 0x01 /* when running UP instead of SMP */
7 #define ALT_COND_NO_DCACHE 0x02 /* if system has no d-cache */
8 #define ALT_COND_NO_ICACHE 0x04 /* if system has no i-cache */
24 s32 orig_offset; /* offset to original instructions */
35 /* Alternative SMP implementation. */
39 ".word (0b-4-.) !" \
50 .word (from - .) ! \
51 .hword (to - from)/4, cond ! \
59 .word (from - .) ! \
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/linux/arch/x86/include/asm/numachip/
H A Dnumachip_csr.h6 * Numascale NumaConnect-Specific Header file
17 #include <linux/smp.h>
24 /* 32K CSR space, b15 indicates geo/non-geo */
36 #define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
39 static inline void *lcsr_address(unsigned long offset) in lcsr_address() argument
42 CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK)); in lcsr_address()
45 static inline unsigned int read_lcsr(unsigned long offset) in read_lcsr() argument
47 return swab32(readl(lcsr_address(offset))); in read_lcsr()
50 static inline void write_lcsr(unsigned long offset, unsigned int val) in write_lcsr() argument
52 writel(swab32(val), lcsr_address(offset)); in write_lcsr()
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/linux/arch/powerpc/platforms/8xx/
H A Dmicropatch.c1 // SPDX-License-Identifier: GPL-2.0
324 static void __init cpm_write_patch(cpm8xx_t *cp, int offset, uint *patch, int len) in cpm_write_patch() argument
328 memcpy_toio(cp->cp_dpmem + offset, patch, len); in cpm_write_patch()
333 out_be16(&cp->cp_rccr, 0); in cpm_load_patch()
345 iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; in cpm_load_patch()
346 out_be16(&iip->iic_rpbase, rpbase); in cpm_load_patch()
348 /* Put SPI above the IIC, also 32-byte aligned. */ in cpm_load_patch()
349 spp = (struct spi_pram *)&cp->cp_dparam[PROFF_SPI]; in cpm_load_patch()
350 out_be16(&spp->rpbase, (rpbase + sizeof(iic_t) + 31) & ~31); in cpm_load_patch()
353 smc_uart_t *smp; in cpm_load_patch() local
[all …]
/linux/arch/powerpc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 def_bool PPC64 && $(cc-option, -mabi=elfv2)
8 def_bool PPC64 && $(cc-option, -mcpu=power10 -mprefixed)
11 # Clang has a bug (https://github.com/llvm/llvm-project/issues/62372)
12 # where pcrel code is not generated if -msof
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