Lines Matching +full:smp +full:- +full:offset
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
12 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
14 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
16 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
18 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
20 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
25 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
50 /* returns the offset of the flow controller halt register for a cpu */
59 /* returns the offset of the flow controller csr register for a cpu */
74 /* loads a 32-bit value into a register without a data access */
88 /* Macro to exit SMP coherency. */
91 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW