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/linux/drivers/net/dsa/realtek/
H A Drealtek-smi.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek Simple Management Interface (SMI) driver
5 * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels
6 * but the protocol is not MDIO at all. Instead it is a Realtek
7 * pecularity that need to bit-bang the lines in a special way to
12 * RTL8366 - The original version, apparently
13 * RTL8369 - Similar enough to have the same datsheet as RTL8366
14 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
16 * RTL8366S - Is this "RTL8366 super"?
17 * RTL8367 - Has an OpenWRT driver as well
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 bool "Realtek MDIO interface support"
23 through MDIO.
26 bool "Realtek SMI interface support"
30 through SMI.
37 Select to enable support for Realtek RTL8365MB-VC and RTL8367S.
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_NET_DSA_REALTEK) += realtek_dsa.o
3 realtek_dsa-objs := rtl83xx.o
6 realtek_dsa-objs += realtek-mdio.o
10 realtek_dsa-objs += realtek-smi.o
13 obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o
14 rtl8366-objs := rtl8366-core.o rtl8366rb.o
16 rtl8366-objs += rtl8366rb-leds.o
18 obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o
H A Drealtek-mdio.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek MDIO interface driver
6 * RTL8366 - The original version, apparently
7 * RTL8369 - Similar enough to have the same datsheet as RTL8366
8 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
10 * RTL8366S - Is this "RTL8366 super"?
11 * RTL8367 - Has an OpenWRT driver as well
12 * RTL8368S - Seems to be an alternative name for RTL8366RB
13 * RTL8370 - Also uses SMI
19 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
[all …]
H A Drtl83xx.c1 // SPDX-License-Identifier: GPL-2.0+
11 * rtl83xx_lock() - Locks the mutex used by regmaps
19 * Context: Can sleep. Holds priv->map_lock lock.
26 mutex_lock(&priv->map_lock); in rtl83xx_lock()
31 * rtl83xx_unlock() - Unlocks the mutex used by regmaps
36 * Context: Releases priv->map_lock lock.
43 mutex_unlock(&priv->map_lock); in rtl83xx_unlock()
49 struct realtek_priv *priv = bus->priv; in rtl83xx_user_mdio_read()
51 return priv->ops->phy_read(priv, addr, regnum); in rtl83xx_user_mdio_read()
57 struct realtek_priv *priv = bus->priv; in rtl83xx_user_mdio_write()
[all …]
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - vi
[all...]
H A Drtl8366rb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
27 #include "realtek-smi.h"
28 #include "realtek-mdio.h"
47 /* Switch per-por
[all...]
/linux/drivers/net/ethernet/marvell/
H A Dmvmdio.c2 * Driver for the MDIO interface of Marvell network interfaces.
4 * Since the MDIO interface of Marvell network interfaces is shared
7 * ports, but they in fact share the same SMI interface to access
8 * the MDIO bus). This driver is currently used by the mvneta and
13 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
64 * SMI Timeout measurements:
65 * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
66 * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
76 * but also reflects SMI completion), use that to wait for
77 * SMI access completion instead of polling the SMI busy bit.
[all …]
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mdio.txt1 * System Management Interface (SMI) / MDIO
4 - compatible: One of:
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
13 - #address-cells: Must be <1>.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
20 mdio@1180000001800 {
21 compatible = "cavium,octeon-3860-mdio";
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-98dx3236-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
45 mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
24 mpp6 6 gpio, dev(cs3), xsmi(mdio)
35 mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-asus-rt-ac88u.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "bcm47094-asus-rt-ac3100.dtsi"
11 compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
12 model = "ASUS RT-AC88U";
16 #nvmem-cell-cells = <1>;
22 mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
23 mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
24 reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
25 realtek,disable-leds;
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-39x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include "pinctrl-mvebu.h"
45 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
50 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
54 MPP_VAR_FUNCTION(7, "xsmi", "mdio", V_88F6920_PLUS)),
107 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
124 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
363 .compatible = "marvell,mv88f6920-pinctrl",
367 .compatible = "marvell,mv88f6925-pinctrl",
[all …]
H A Dpinctrl-armada-xp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
26 #include "pinctrl-mvebu.h"
189 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
235 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
243 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
371 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
467 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
471 MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS),
472 MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS),
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Ddove-cm-a510.dtsi2 * Device Tree include for Compulab CM-A510 System-on-Module
6 * This file is dual-licensed: you can use it either under the terms
46 * The CM-A510 comes with several optional components:
56 * E1: PHY RTL8211D on internal GbE (SMI address 0x03)
66 * U2: 2 dual-role USB2.0 ports
70 * W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1)
72 * GPIOs used on CM-A510:
86 model = "Compulab CM-A510";
87 compatible = "compulab,cm-a510", "marvell,dove";
99 compatible = "gpio-leds";
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dcharon.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 /dts-v1/;
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&mpc5200_pic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
28 d-cache-line-size = <32>;
29 i-cache-line-size = <32>;
30 d-cache-size = <0x4000>; // L1, 16K
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
[all …]
/linux/arch/mips/cavium-octeon/
H A Docteon-platform.c6 * Copyright (C) 2004-2017 Cavium, Inc.
19 #include <asm/octeon/cvmx-helper-board.h>
25 #include <asm/octeon/cvmx-uctlx-defs.h>
79 if (dev->of_node) { in octeon2_usb_clocks_start()
83 uctl_node = of_get_parent(dev->of_node); in octeon2_usb_clocks_start()
89 "refclk-frequency", &clock_rate); in octeon2_usb_clocks_start()
91 dev_err(dev, "No UCTL \"refclk-frequency\"\n"); in octeon2_usb_clocks_start()
96 "refclk-type", &clock_type); in octeon2_usb_clocks_start()
204 * Step 4: Program the power-on reset field in the UCTL in octeon2_usb_clocks_start()
205 * clock-reset-control register. in octeon2_usb_clocks_start()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
53 VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
134 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status()
144 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status()
210 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status_fiber()
220 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status_fiber()
276 * Enable/disable auto MDI/MDI-X in forced link speed mode.
376 SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T"); in t3_vsc8211_phy_prep()
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz_common.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2025 Microchip Technology Inc.
14 #include <linux/platform_data/microchip-ksz.h>
206 * struct ksz_drive_strength - drive strength mapping
215 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
223 * - for high speed signals
233 * - for low speed signals
250 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
270 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy)
281 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy)
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-drv.c1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
20 #include "xgbe-common.h"
67 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) { in xgbe_free_channels()
68 if (!pdata->channel[i]) in xgbe_free_channels()
71 kfree(pdata->channel[i]->rx_ring); in xgbe_free_channels()
72 kfree(pdata->channel[i]->tx_ring); in xgbe_free_channels()
73 kfree(pdata->channel[i]); in xgbe_free_channels()
75 pdata->channel[i] = NULL; in xgbe_free_channels()
78 pdata->channel_count = 0; in xgbe_free_channels()
[all …]

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