Lines Matching +full:smi +full:- +full:mdio
1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
11 * (SMI), which uses the MDIO/MDC lines.
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC |
22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension |
25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ |
26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ |
29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ |
31 * Interrupt <----------> Link UP/DOWN events |
33 * '-----------------------------------'
38 * partner of the extension port - either via a fixed-link or other phy-handle.
40 * driver has only been tested with a fixed-link, but in principle it should not
47 * the status registers via SMI. Interrupts are then propagated to the relevant
55 * This Linux driver is written based on an OS-agnostic vendor driver from
56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt
59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under
61 * common hardware revision, there exist examples of chips with the suffix -VC
72 * - RTL8363NB
73 * - RTL8363NB-VB
74 * - RTL8363SC
75 * - RTL8363SC-VB
76 * - RTL8364NB
77 * - RTL8364NB-VB
78 * - RTL8365MB-VC
79 * - RTL8366SC
80 * - RTL8367RB-VB
81 * - RTL8367SB
82 * - RTL8367S
83 * - RTL8370MB
84 * - RTL8310SR
88 * things will work out-of-the-box for other chips, and a careful review of the
89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be
104 #include "realtek-smi.h"
105 #include "realtek-mdio.h"
108 /* Family-specific data and limits */
111 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
135 /* Interrupt control/status register - enable/check specific interrupt types */
164 /* Per-port interrupt type status registers */
195 /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */
235 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */
257 /* CPU port mask register - controls which ports are treated as CPU ports */
287 /* MSTP port state registers - indexed by tree instance */
485 * struct rtl8365mb_extint - external interface info
490 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded
500 * struct rtl8365mb_chip_info - static chip-specific info
501 * @name: human-readable chip name
505 * @jam_table: chip-specific initialization jam table
525 .name = "RTL8365MB-VC",
548 .name = "RTL8367RB-VB",
591 * struct rtl8365mb_cpu - CPU port configuration
592 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames
595 * @insert: CPU tag insertion mode in switch->CPU frames
614 * struct rtl8365mb_port - private per-port data
631 * struct rtl8365mb - driver private data
634 * @chip_info: chip-specific info about the attached switch
637 * @ports: per-port data
654 return regmap_read_poll_timeout(priv->map_nolock,
668 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG,
681 ret = regmap_write(priv->map_nolock,
710 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
720 ret = regmap_read(priv->map_nolock,
750 ret = regmap_write(priv->map_nolock,
760 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
782 return -EINVAL;
785 return -EINVAL;
791 dev_err(priv->dev,
797 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",
810 return -EINVAL;
813 return -EINVAL;
819 dev_err(priv->dev,
825 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",
834 struct rtl8365mb *mb = priv->chip_data;
839 &mb->chip_info->extints[i];
841 if (!extint->supported_interfaces)
844 if (extint->port == port)
855 struct realtek_priv *priv = ds->priv;
859 mb = priv->chip_data;
860 cpu = &mb->cpu;
862 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC)
873 struct dsa_switch *ds = &priv->ds;
882 return -ENODEV;
885 dn = dp->dn;
904 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is
906 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only
909 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) {
915 dev_warn(priv->dev,
919 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) {
925 dev_warn(priv->dev,
930 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id),
939 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id),
940 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id),
943 extint->id));
965 return -ENODEV;
980 dev_err(priv->dev, "unsupported port speed %s\n",
982 return -EINVAL;
990 dev_err(priv->dev, "unsupported duplex %s\n",
992 return -EINVAL;
1012 ret = regmap_write(priv->map,
1013 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id),
1025 rtl8365mb_get_port_extint(ds->priv, port);
1027 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
1032 config->supported_interfaces);
1038 config->supported_interfaces);
1047 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII)
1048 phy_interface_set_rgmii(config->supported_interfaces);
1056 struct realtek_priv *priv = dp->ds->priv;
1057 u8 port = dp->index;
1061 dev_err(priv->dev,
1062 "port %d supports only conventional PHY or fixed-link\n",
1067 if (phy_interface_mode_is_rgmii(state->interface)) {
1068 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface);
1070 dev_err(priv->dev,
1076 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also
1086 struct realtek_priv *priv = dp->ds->priv;
1089 u8 port = dp->index;
1092 mb = priv->chip_data;
1093 p = &mb->ports[port];
1094 cancel_delayed_work_sync(&p->mib_work);
1100 dev_err(priv->dev,
1116 struct realtek_priv *priv = dp->ds->priv;
1119 u8 port = dp->index;
1122 mb = priv->chip_data;
1123 p = &mb->ports[port];
1124 schedule_delayed_work(&p->mib_work, 0);
1131 dev_err(priv->dev,
1142 struct realtek_priv *priv = ds->priv;
1154 dev_dbg(priv->dev, "changing mtu to %d (frame size: %d)\n",
1157 return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,
1165 return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN;
1171 struct realtek_priv *priv = ds->priv;
1190 dev_err(priv->dev, "invalid STP state: %u\n", state);
1194 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port),
1207 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),
1214 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);
1229 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG,
1235 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val,
1243 return -EIO;
1257 ret = regmap_read(priv->map,
1258 RTL8365MB_MIB_COUNTER_REG(offset - i), &val);
1273 struct realtek_priv *priv = ds->priv;
1278 mb = priv->chip_data;
1280 mutex_lock(&mb->mib_lock);
1284 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1285 mib->length, &data[i]);
1287 dev_err(priv->dev,
1293 mutex_unlock(&mb->mib_lock);
1305 ethtool_puts(&data, mib->name);
1312 return -EOPNOTSUPP;
1320 struct realtek_priv *priv = ds->priv;
1324 mb = priv->chip_data;
1327 mutex_lock(&mb->mib_lock);
1328 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1329 &phy_stats->SymbolErrorDuringCarrier);
1330 mutex_unlock(&mb->mib_lock);
1356 struct realtek_priv *priv = ds->priv;
1361 mb = priv->chip_data;
1363 mutex_lock(&mb->mib_lock);
1371 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1372 mib->length, &cnt[i]);
1376 mutex_unlock(&mb->mib_lock);
1378 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into
1384 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1387 cnt[RTL8365MB_MIB_dot3OutPauseFrames] -
1389 mac_stats->SingleCollisionFrames =
1391 mac_stats->MultipleCollisionFrames =
1393 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1397 mac_stats->FrameCheckSequenceErrors =
1399 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] -
1400 18 * mac_stats->FramesTransmittedOK;
1401 mac_stats->FramesWithDeferredXmissions =
1403 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1404 mac_stats->FramesAbortedDueToXSColls =
1406 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] -
1407 18 * mac_stats->FramesReceivedOK;
1408 mac_stats->MulticastFramesXmittedOK =
1410 mac_stats->BroadcastFramesXmittedOK =
1412 mac_stats->MulticastFramesReceivedOK =
1414 mac_stats->BroadcastFramesReceivedOK =
1421 struct realtek_priv *priv = ds->priv;
1425 mb = priv->chip_data;
1428 mutex_lock(&mb->mib_lock);
1429 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1430 &ctrl_stats->UnsupportedOpcodesReceived);
1431 mutex_unlock(&mb->mib_lock);
1453 struct rtl8365mb *mb = priv->chip_data;
1458 stats = &mb->ports[port].stats;
1460 mutex_lock(&mb->mib_lock);
1468 ret = rtl8365mb_mib_counter_read(priv, port, c->offset,
1469 c->length, &cnt[i]);
1473 mutex_unlock(&mb->mib_lock);
1479 spin_lock(&mb->ports[port].stats_lock);
1481 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1483 cnt[RTL8365MB_MIB_ifInBroadcastPkts] -
1486 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1490 /* if{In,Out}Octets includes FCS - remove it */
1491 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets;
1492 stats->tx_bytes =
1493 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets;
1495 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents];
1496 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards];
1498 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts];
1499 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions];
1501 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] +
1503 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1504 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors;
1506 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards];
1507 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1508 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors;
1510 spin_unlock(&mb->ports[port].stats_lock);
1518 struct realtek_priv *priv = p->priv;
1520 rtl8365mb_stats_update(priv, p->index);
1522 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES);
1528 struct realtek_priv *priv = ds->priv;
1532 mb = priv->chip_data;
1533 p = &mb->ports[port];
1535 spin_lock(&p->stats_lock);
1536 memcpy(s, &p->stats, sizeof(*s));
1537 spin_unlock(&p->stats_lock);
1542 struct rtl8365mb *mb = priv->chip_data;
1543 struct dsa_switch *ds = &priv->ds;
1546 /* Per-chip global mutex to protect MIB counter access, since doing
1549 mutex_init(&mb->mib_lock);
1551 for (i = 0; i < priv->num_ports; i++) {
1552 struct rtl8365mb_port *p = &mb->ports[i];
1557 /* Per-port spinlock to protect the stats64 data */
1558 spin_lock_init(&p->stats_lock);
1561 * up-to-date.
1563 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll);
1569 struct rtl8365mb *mb = priv->chip_data;
1570 struct dsa_switch *ds = &priv->ds;
1573 for (i = 0; i < priv->num_ports; i++) {
1574 struct rtl8365mb_port *p = &mb->ports[i];
1579 cancel_delayed_work_sync(&p->mib_work);
1588 ret = regmap_read(priv->map, reg, val);
1592 return regmap_write(priv->map, reg, *val);
1633 for_each_set_bit(line, &line_changes, priv->num_ports) {
1634 int child_irq = irq_find_mapping(priv->irqdomain, line);
1642 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret);
1650 /* The hardware doesn't support masking IRQs on a per-port basis */
1656 irq_set_chip_data(irq, domain->host_data);
1679 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG,
1697 struct rtl8365mb *mb = priv->chip_data;
1706 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
1708 dev_err(priv->dev, "missing child interrupt-controller node\n");
1709 return -EINVAL;
1715 if (irq != -EPROBE_DEFER)
1716 dev_err(priv->dev, "failed to get parent irq: %d\n",
1718 ret = irq ? irq : -EINVAL;
1722 priv->irqdomain = irq_domain_create_linear(of_fwnode_handle(intc), priv->num_ports,
1724 if (!priv->irqdomain) {
1725 dev_err(priv->dev, "failed to add irq domain\n");
1726 ret = -ENOMEM;
1730 for (i = 0; i < priv->num_ports; i++) {
1731 virq = irq_create_mapping(priv->irqdomain, i);
1733 dev_err(priv->dev,
1735 ret = -EINVAL;
1754 dev_err(priv->dev, "unsupported irq trigger type %u\n",
1756 ret = -EINVAL;
1760 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG,
1772 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG,
1780 dev_err(priv->dev, "failed to request irq: %d\n", ret);
1785 mb->irq = irq;
1796 free_irq(mb->irq, priv);
1797 mb->irq = 0;
1800 for (i = 0; i < priv->num_ports; i++) {
1801 virq = irq_find_mapping(priv->irqdomain, i);
1805 irq_domain_remove(priv->irqdomain);
1806 priv->irqdomain = NULL;
1816 struct rtl8365mb *mb = priv->chip_data;
1820 if (mb->irq) {
1821 free_irq(mb->irq, priv);
1822 mb->irq = 0;
1825 if (priv->irqdomain) {
1826 for (i = 0; i < priv->num_ports; i++) {
1827 virq = irq_find_mapping(priv->irqdomain, i);
1831 irq_domain_remove(priv->irqdomain);
1832 priv->irqdomain = NULL;
1838 struct rtl8365mb *mb = priv->chip_data;
1839 struct rtl8365mb_cpu *cpu = &mb->cpu;
1843 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG,
1846 cpu->mask));
1850 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |
1851 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) |
1852 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) |
1853 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) |
1854 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) |
1855 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) |
1857 cpu->trap_port >> 3 & 0x1);
1858 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val);
1868 struct realtek_priv *priv = ds->priv;
1872 mb = priv->chip_data;
1873 cpu = &mb->cpu;
1877 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1878 cpu->position = RTL8365MB_CPU_POS_AFTER_SA;
1881 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1882 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC;
1884 /* The switch also supports a 4-byte format, similar to rtl4a but with
1885 * the same 0x04 8-bit version and probably 8-bit port source/dest.
1890 return -EPROTONOSUPPORT;
1898 struct rtl8365mb *mb = priv->chip_data;
1903 ci = mb->chip_info;
1905 /* Do any chip-specific init jam before getting to the common stuff */
1906 if (ci->jam_table) {
1907 for (i = 0; i < ci->jam_size; i++) {
1908 ret = regmap_write(priv->map, ci->jam_table[i].reg,
1909 ci->jam_table[i].val);
1917 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg,
1930 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG,
1937 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,
1944 struct realtek_priv *priv = ds->priv;
1951 mb = priv->chip_data;
1952 cpu = &mb->cpu;
1956 dev_err(priv->dev, "failed to reset chip: %d\n", ret);
1960 /* Configure switch to vendor-defined initial state */
1963 dev_err(priv->dev, "failed to initialize switch: %d\n", ret);
1969 if (ret == -EPROBE_DEFER)
1972 dev_info(priv->dev, "no interrupt support\n");
1976 cpu->mask |= BIT(cpu_dp->index);
1978 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS)
1979 cpu->trap_port = cpu_dp->index;
1981 cpu->enable = cpu->mask > 0;
1987 for (i = 0; i < priv->num_ports; i++) {
1988 struct rtl8365mb_port *p = &mb->ports[i];
1994 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask);
2009 /* Set up per-port private data */
2010 p->priv = priv;
2011 p->index = i;
2014 ret = rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN);
2020 dev_err(priv->dev, "could not set up MDIO bus\n");
2038 struct realtek_priv *priv = ds->priv;
2073 struct rtl8365mb *mb = priv->chip_data;
2079 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver);
2081 dev_err(priv->dev, "failed to read chip id and version: %d\n",
2089 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) {
2090 mb->chip_info = ci;
2095 if (!mb->chip_info) {
2096 dev_err(priv->dev,
2099 return -ENODEV;
2102 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name);
2104 priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
2105 mb->priv = priv;
2106 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;
2107 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
2108 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
2109 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
2110 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;
2165 .name = "rtl8365mb-smi",
2175 .name = "rtl8365mb-mdio",
2208 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>");
2209 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch");