Lines Matching +full:smi +full:- +full:mdio
1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
27 #include "realtek-smi.h"
28 #include "realtek-mdio.h"
47 /* Switch per-port learning disablement register */
160 * VID such as untagged or priority-tagged frames for respective
163 * a C-tag with VID != 0 for respective port.
363 mib->offset;
368 ret = regmap_write(priv->map, addr, 0); /* Write whatever */
373 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
375 return -EIO;
378 return -EBUSY;
381 return -EIO;
385 for (i = mib->length; i > 0; i--) {
386 ret = regmap_read(priv->map, addr + (i - 1), &val);
414 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
417 dev_err(priv->dev, "could not mask IRQ\n");
425 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
429 dev_err(priv->dev, "could not unmask IRQ\n");
439 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
442 dev_err(priv->dev, "can't read interrupt status\n");
457 line -= 5;
458 child_irq = irq_find_mapping(priv->irqdomain, line);
473 irq_set_chip_data(irq, domain->host_data);
503 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
505 dev_err(priv->dev, "missing child interrupt-controller node\n");
506 return -EINVAL;
511 dev_err(priv->dev, "failed to get parent IRQ\n");
512 ret = irq ? irq : -EINVAL;
517 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
520 dev_err(priv->dev, "can't read interrupt status\n");
529 dev_info(priv->dev, "active high/rising IRQ\n");
534 dev_info(priv->dev, "active low/falling IRQ\n");
538 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
542 dev_err(priv->dev, "could not configure IRQ polarity\n");
546 ret = devm_request_threaded_irq(priv->dev, irq, NULL,
550 dev_err(priv->dev, "unable to request irq: %d\n", ret);
553 priv->irqdomain = irq_domain_create_linear(of_fwnode_handle(intc), RTL8366RB_NUM_INTERRUPT,
555 if (!priv->irqdomain) {
556 dev_err(priv->dev, "failed to create IRQ domain\n");
557 ret = -EINVAL;
560 for (i = 0; i < priv->num_ports; i++)
561 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
576 dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
579 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
583 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
587 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
635 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
650 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
686 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
728 ret = regmap_read(priv->map,
734 ret = regmap_write(priv->map,
742 dev_dbg(priv->dev, "jam %04x into register %04x\n",
745 ret = regmap_write(priv->map,
764 ret = regmap_update_bits(priv->map,
780 regmap_update_bits(priv->map,
797 struct realtek_priv *priv = ds->priv;
806 rb = priv->chip_data;
808 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
810 dev_err(priv->dev, "unable to read chip id\n");
818 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
819 return -ENODEV;
822 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
825 dev_err(priv->dev, "unable to read chip version\n");
829 dev_info(priv->dev, "RTL%04x ver %u chip found\n",
854 * without them, using just the off-the-shelf tables.
856 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
872 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
879 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
891 ret = regmap_write(priv->map,
898 ret = regmap_write(priv->map, 0x0c, 0x240);
901 ret = regmap_write(priv->map, 0x0d, 0x240);
915 ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,
917 BIT(priv->cpu_port));
921 /* Make sure we default-enable the fixed CPU port */
922 ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
923 BIT(priv->cpu_port),
929 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
935 if (i == priv->cpu_port)
937 rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
939 rb->max_mtu[i] = ETH_DATA_LEN;
943 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
949 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
960 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
966 /* Accept all packets by default, we enable filtering on-demand */
967 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
971 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
977 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
985 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
997 if (priv->leds_disabled) {
1013 dev_info(priv->dev, "no interrupt support\n");
1017 dev_err(priv->dev, "could not set up MDIO bus\n");
1018 return -ENODEV;
1035 unsigned long *interfaces = config->supported_interfaces;
1036 struct realtek_priv *priv = ds->priv;
1038 if (port == priv->cpu_port) {
1046 config->mac_capabilities = MAC_1000 | MAC_100 |
1053 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1070 struct realtek_priv *priv = dp->ds->priv;
1071 int port = dp->index;
1076 * We assume autonegotiation works on the PHY-facing ports.
1078 if (port != priv->cpu_port)
1081 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1083 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1086 dev_err(priv->dev, "failed to force CPU port\n");
1117 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1121 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1125 dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1128 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1131 dev_err(priv->dev, "failed to enable the CPU port\n");
1141 struct realtek_priv *priv = dp->ds->priv;
1142 int port = dp->index;
1145 if (port != priv->cpu_port)
1148 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1151 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1154 dev_err(priv->dev, "failed to disable the CPU port\n");
1163 struct realtek_priv *priv = ds->priv;
1166 dev_dbg(priv->dev, "enable port %d\n", port);
1167 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1178 struct realtek_priv *priv = ds->priv;
1181 dev_dbg(priv->dev, "disable port %d\n", port);
1182 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1194 struct realtek_priv *priv = ds->priv;
1207 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1211 dev_err(priv->dev, "failed to join port %d\n", port);
1217 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1226 struct realtek_priv *priv = ds->priv;
1239 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1242 dev_err(priv->dev, "failed to leave port %d\n", port);
1248 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1253 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1254 * @priv: SMI state container
1255 * @port: the port to drop untagged and C-tagged frames on
1256 * @drop: whether to drop or pass untagged and C-tagged frames
1262 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1271 struct realtek_priv *priv = ds->priv;
1275 rb = priv->chip_data;
1277 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1281 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1287 * not drop any untagged or C-tagged frames. If we turn off VLAN
1291 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1305 return -EINVAL;
1315 struct realtek_priv *priv = ds->priv;
1319 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1332 struct realtek_priv *priv = ds->priv;
1351 dev_err(priv->dev, "unknown bridge state requested\n");
1357 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1366 struct realtek_priv *priv = ds->priv;
1369 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1372 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1378 struct realtek_priv *priv = ds->priv;
1384 /* Cache the per-port MTU setting */
1385 rb = priv->chip_data;
1386 rb->max_mtu[port] = new_mtu;
1394 if (rb->max_mtu[i] > max_mtu)
1395 max_mtu = rb->max_mtu[i];
1418 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1427 * 16000 - 18 - 4 = 15978. This does not include the CPU tag
1430 return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1443 return -EINVAL;
1446 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1452 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1458 ret = regmap_read(priv->map,
1465 vlan4k->vid = vid;
1466 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1468 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1469 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1481 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1482 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1483 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1484 vlan4k->fid > RTL8366RB_FIDMAX)
1485 return -EINVAL;
1487 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1488 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1489 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1491 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1494 ret = regmap_write(priv->map,
1502 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1518 return -EINVAL;
1521 ret = regmap_read(priv->map,
1528 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1529 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1531 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1533 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1534 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1547 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1548 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1549 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1550 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1551 vlanmc->fid > RTL8366RB_FIDMAX)
1552 return -EINVAL;
1554 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1555 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1557 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1558 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1560 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1563 ret = regmap_write(priv->map,
1578 if (port >= priv->num_ports)
1579 return -EINVAL;
1581 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1594 struct dsa_switch *ds = &priv->ds;
1599 rb = priv->chip_data;
1602 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1603 return -EINVAL;
1605 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1613 rb->pvid_enabled[port] = pvid_enabled;
1616 * not drop any untagged or C-tagged frames. Make sure to update the
1627 unsigned int max = RTL8366RB_NUM_VLANS - 1;
1629 if (priv->vlan4k_enabled)
1630 max = RTL8366RB_NUM_VIDS - 1;
1640 dev_dbg(priv->dev, "%s VLAN\n", str_enable_disable(enable));
1641 return regmap_update_bits(priv->map,
1648 dev_dbg(priv->dev, "%s VLAN 4k\n", str_enable_disable(enable));
1649 return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1661 return -EINVAL;
1665 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1672 ret = regmap_write(priv->map_nolock, reg, 0);
1674 dev_err(priv->dev,
1680 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1687 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1703 return -EINVAL;
1707 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1714 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1717 ret = regmap_write(priv->map_nolock, reg, val);
1733 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1737 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1743 } while (--timeout);
1746 dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1747 return -EIO;
1755 struct device *dev = priv->dev;
1760 ret = regmap_read(priv->map, 0x5c, &val);
1770 return -ENODEV;
1773 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1774 priv->num_ports = RTL8366RB_NUM_PORTS;
1775 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1776 priv->mib_counters = rtl8366rb_mib_counters;
1777 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1856 .name = "rtl8366rb-smi",
1866 .name = "rtl8366rb-mdio",