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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dste,nomadik.txt4 - compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
5 "stericsson,stn8815-pinctrl"
6 - nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
8 - prcm: phandle to the PRCMU managing the back end of this pin controller
10 Please refer to pinctrl-bindings.txt in this directory for details of the
23 (see pinctrl-bindings.txt):
26 - function: A string containing the name of the function to mux to the
28 - groups : An array of strings. Each string contains the name of a pin
30 set-up.
33 - pins: A string array describing the pins affected by the configuration
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa2xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
5 * Taken from pxa-regs.h by Russell King
14 #include "pxa-regs.h"
21 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
23 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
24 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
25 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
26 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
28 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
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/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson
5 #include <dt-bindings/pinctrl/nomadik.h>
29 ste,gpio = <GPIOMODE_ENABLED>;
34 ste,gpio = <GPIOMODE_ENABLED>;
39 ste,gpio = <GPIOMODE_ENABLED>;
44 ste,gpio = <GPIOMODE_ENABLED>;
49 ste,gpio = <GPIOMODE_ENABLED>;
54 ste,sleep = <SLPM_ENABLED>;
55 ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
[all …]
H A Dste-snowball.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 ST-Ericsson AB
6 /dts-v1/;
7 #include "ste-db9500.dtsi"
8 #include "ste-href-ab8500.dtsi"
9 #include "ste-href-family-pinctrl.dtsi"
13 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
21 compatible = "simple-battery";
22 battery-type = "lithium-ion-polymer";
25 thermal-zones {
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H A Dstm32mp135f-dhcor-dhsbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
7 * DHCOR PCB number: 718-100 or newer
8 * DHSBC PCB number: 719-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
16 #include "stm32mp13xx-dhcor-som.dtsi"
20 compatible = "dh,stm32mp135f-dhcor-dhsbc",
21 "dh,stm32mp135f-dhcor-som",
32 stdout-path = "serial0:115200n8";
[all …]
H A Dste-ux500-samsung-skomer.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer.
6 /dts-v1/;
7 #include "ste-db8500.dtsi"
8 #include "ste-ab8505.dtsi"
9 #include "ste-dbx5x0-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
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H A Dste-ux500-samsung-golden.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include "ste-db8500.dtsi"
5 #include "ste-ab8505.dtsi"
6 #include "ste-dbx5x0-pinctrl.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 * You need an intermediate, device-tree compatible bootloader
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H A Dstm32mp151c-plyaqm.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /dts-v1/;
6 #include <arm/st/stm32mp15-pinctrl.dtsi>
7 #include <arm/st/stm32mp15xxad-pinctrl.dtsi>
8 #include <arm/st/stm32mp15-scmi.dtsi>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
27 remote-endpoint = <&i2s1_endpoint>;
28 dai-format = "i2s";
35 compatible = "linaro,optee-tz";
[all …]
H A Dste-ux500-samsung-kyle.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy Amp SGH-I407 also known as Kyle.
10 /dts-v1/;
11 #include "ste-db8500.dtsi"
12 #include "ste-ab8505.dtsi"
13 #include "ste-dbx5x0-pinctrl.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
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H A Dstm32mp157c-ultra-fly-sbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Ultratronik GmbH 2024-2025 - All Rights Reserved
6 /dts-v1/;
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "ultratronik,stm32mp157c-ultra-fly-sbc", "st,stm32mp157";
28 stdout-path = "serial0:115200n8";
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H A Dstm32mp133c-prihmb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
10 #include "stm32mp13-pinctrl.dtsi"
13 model = "Priva E-Measuringbox board";
18 mdio-gpio0 = &mdio0;
27 stdout-path = "serial0:115200n8";
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H A Dstm32mp15x-mecio1-io.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include "stm32mp15-pinctrl.dtsi"
9 #include "stm32mp15xxaa-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
15 stdout-path = "serial0:1500000n8";
34 reserved-memory {
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "shared-dma-pool";
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H A Dste-ux500-samsung-gavini.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy Beam GT-I8530 also known as Gavini.
6 /dts-v1/;
7 #include "ste-db8500.dtsi"
8 #include "ste-ab8500.dtsi"
9 #include "ste-dbx5x0-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
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/linux/Documentation/admin-guide/
H A Dbtmrvl.rst13 These commands are used to configure the host sleep parameters::
14 bit 8:0 -- Gap
15 bit 16:8 -- GPIO
17 where GPIO is the pin number of GPIO used to wake up the host.
18 It could be any valid GPIO pin# (e.g. 0-7) or 0xff (SDIO interface
22 wakeup event, or 0xff for special host sleep setting.
30 # Use GPIO pin #3 to wake up the host and set GAP to 0xff:
35 These commands are used to enable/disable auto sleep mode
39 1 -- Enable auto sleep mode
40 0 -- Disable auto sleep mode
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdcc1_default_state: sdcc1-default-state {
5 clk-pins {
7 drive-strength = <16>;
8 bias-disable;
11 cmd-pins {
13 drive-strength = <10>;
14 bias-pull-up;
17 data-pins {
19 drive-strength = <10>;
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-nexus7-grouper-ti-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
13 #interrupt-cells = <2>;
14 interrupt-controller;
15 wakeup-source;
17 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
18 ti,system-power-controller;
19 ti,sleep-keep-ck32k;
20 ti,sleep-enable;
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/linux/arch/powerpc/boot/dts/
H A Dmpc8379_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
33 i-cache-size = <32768>;
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H A Dmpc8377_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <32768>;
35 i-cache-size = <32768>;
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H A Dmpc8377_wlan.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2009 Freescale Semiconductor Inc.
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
16 interrupt-parent = <&intc>;
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H A Dapq8016-schneider-hmibsc.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
9 #include "msm8916-pm8916.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
15 #include <dt-bindings/sound/apq8016-lpass.h>
19 compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";
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/linux/drivers/net/wireless/marvell/mwifiex/
H A DREADME2 # Copyright 2011-2020 NXP
9 # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
10 # worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
12 # THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
38 Following are some useful iw commands:-
45 iw dev mlan0 connect -w <SSID> [<freq in MHz>] [<bssid>] [key 0:abcde d:1123456789a]
55 iw dev mlan0 ibss join <SSID> <freq in MHz> [fixed-freq] [fixed-bssid] [key 0:abcde]
79 mount -t debugfs debugfs /debugfs
98 bss_mode = "Ad-hoc" | "Managed" | "Auto" | "Unknown"
100 mac_address = <6-byte adapter MAC address>
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/linux/arch/arm/mach-s3c/
H A Dpm.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include "pm-common.h"
36 /* configuration for the IRQ mask over sleep */
40 /* per-cpu sleep functions */
49 /* from sleep.S */
66 * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
68 * Setup all the necessary GPIO pins for waking the system on external
75 * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
77 * Restore the state of the GPIO pins after sleep, which may involve ensuring
84 * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-speedy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "rk3288-veyron-broadcom-bluetooth.dtsi"
11 #include "../cros-ec-sbs.dtsi"
15 compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
16 "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
17 "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
18 "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
19 "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
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H A Drk3288-veyron-jaq.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "rk3288-veyron-chromebook.dtsi"
11 #include "../cros-ec-sbs.dtsi"
15 compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
16 "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
17 "google,veyron-jaq-rev1", "google,veyron-jaq",
22 /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
23 brightness-levels = <8 255>;
24 num-interpolated-steps = <247>;
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