1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) Protonic Holland 4 * Author: David Jander <david@protonic.nl> 5 */ 6 7#include "stm32mp15xc.dtsi" 8#include "stm32mp15-pinctrl.dtsi" 9#include "stm32mp15xxaa-pinctrl.dtsi" 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12 13/ { 14 chosen { 15 stdout-path = "serial0:1500000n8"; 16 }; 17 18 aliases { 19 serial0 = &uart4; 20 ethernet0 = ðernet0; 21 spi1 = &spi1; 22 spi2 = &spi2; 23 spi3 = &spi3; 24 spi4 = &spi4; 25 spi5 = &spi5; 26 spi6 = &spi6; 27 }; 28 29 memory@c0000000 { 30 device_type = "memory"; 31 reg = <0xC0000000 0x10000000>; 32 }; 33 34 reserved-memory { 35 #address-cells = <1>; 36 #size-cells = <1>; 37 ranges; 38 39 mcuram2: mcuram2@10000000 { 40 compatible = "shared-dma-pool"; 41 reg = <0x10000000 0x40000>; 42 no-map; 43 }; 44 45 vdev0vring0: vdev0vring0@10040000 { 46 compatible = "shared-dma-pool"; 47 reg = <0x10040000 0x1000>; 48 no-map; 49 }; 50 51 vdev0vring1: vdev0vring1@10041000 { 52 compatible = "shared-dma-pool"; 53 reg = <0x10041000 0x1000>; 54 no-map; 55 }; 56 57 vdev0buffer: vdev0buffer@10042000 { 58 compatible = "shared-dma-pool"; 59 reg = <0x10042000 0x4000>; 60 no-map; 61 }; 62 63 mcuram: mcuram@30000000 { 64 compatible = "shared-dma-pool"; 65 reg = <0x30000000 0x40000>; 66 no-map; 67 }; 68 69 retram: retram@38000000 { 70 compatible = "shared-dma-pool"; 71 reg = <0x38000000 0x10000>; 72 no-map; 73 }; 74 }; 75 76 v3v3: regulator-v3v3 { 77 compatible = "regulator-fixed"; 78 regulator-name = "v3v3"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 }; 82 83 v5v: regulator-v5v { 84 compatible = "regulator-fixed"; 85 regulator-name = "v5v"; 86 regulator-min-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>; 88 regulator-always-on; 89 }; 90}; 91 92&adc { 93 /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ 94 pinctrl-0 = <&adc12_pins_mecsbc>; 95 pinctrl-names = "default"; 96 vdd-supply = <&v3v3>; 97 vdda-supply = <&v3v3>; 98 vref-supply = <&v3v3>; 99 status = "okay"; 100}; 101 102&adc1 { 103 status = "okay"; 104 105 channel@0 { 106 reg = <0>; 107 /* 16.5 ck_cycles sampling time */ 108 st,min-sample-time-ns = <5000>; 109 label = "p24v_stp"; 110 }; 111 112 channel@1 { 113 reg = <1>; 114 st,min-sample-time-ns = <5000>; 115 label = "p24v_hpdcm"; 116 }; 117 118 channel@2 { 119 reg = <2>; 120 st,min-sample-time-ns = <5000>; 121 label = "ain0"; 122 }; 123 124 channel@3 { 125 reg = <3>; 126 st,min-sample-time-ns = <5000>; 127 label = "hpdcm1_i2"; 128 }; 129 130 channel@5 { 131 reg = <5>; 132 st,min-sample-time-ns = <5000>; 133 label = "hpout1_i"; 134 }; 135 136 channel@6 { 137 reg = <6>; 138 st,min-sample-time-ns = <5000>; 139 label = "ain1"; 140 }; 141 142 channel@9 { 143 reg = <9>; 144 st,min-sample-time-ns = <5000>; 145 label = "hpout0_i"; 146 }; 147 148 channel@10 { 149 reg = <10>; 150 st,min-sample-time-ns = <5000>; 151 label = "phint0_ain"; 152 }; 153 154 channel@13 { 155 reg = <13>; 156 st,min-sample-time-ns = <5000>; 157 label = "phint1_ain"; 158 }; 159 160 channel@15 { 161 reg = <15>; 162 st,min-sample-time-ns = <5000>; 163 label = "hpdcm0_i1"; 164 }; 165 166 channel@16 { 167 reg = <16>; 168 st,min-sample-time-ns = <5000>; 169 label = "lsin"; 170 }; 171 172 channel@18 { 173 reg = <18>; 174 st,min-sample-time-ns = <5000>; 175 label = "hpdcm0_i2"; 176 }; 177 178 channel@19 { 179 reg = <19>; 180 st,min-sample-time-ns = <5000>; 181 label = "hpdcm1_i1"; 182 }; 183}; 184 185&adc2 { 186 status = "okay"; 187 188 channel@2 { 189 reg = <2>; 190 /* 16.5 ck_cycles sampling time */ 191 st,min-sample-time-ns = <5000>; 192 label = "ain2"; 193 }; 194 195 channel@6 { 196 reg = <6>; 197 st,min-sample-time-ns = <5000>; 198 label = "ain3"; 199 }; 200}; 201 202ðernet0 { 203 status = "okay"; 204 pinctrl-0 = <ðernet0_rgmii_pins_x>; 205 pinctrl-1 = <ðernet0_rgmii_sleep_pins_x>; 206 pinctrl-names = "default", "sleep"; 207 phy-mode = "rgmii-id"; 208 max-speed = <1000>; 209 phy-handle = <&phy0>; 210 st,eth-clk-sel; 211 212 mdio { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "snps,dwmac-mdio"; 216 phy0: ethernet-phy@8 { 217 reg = <8>; 218 interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; 219 reset-gpios = <&gpiog 10 GPIO_ACTIVE_LOW>; 220 reset-assert-us = <10>; 221 reset-deassert-us = <35>; 222 }; 223 }; 224}; 225 226&gpiod { 227 gpio-line-names = "", "", "", "", 228 "", "", "", "", 229 "", "", "", "", 230 "STP_RESETN", "STP_ENABLEN", "HPOUT0", "HPOUT0_ALERTN"; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_hog_d_mecsbc>; 233}; 234 235&gpioe { 236 gpio-line-names = "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", 237 "", "", "HPOUT1_RESETN", 238 "LPOUT0", "LPOUT0_ALERTN", "GPOUT0_RESETN", 239 "LPOUT1", "LPOUT1_ALERTN", "GPOUT1_RESETN", 240 "LPOUT2", "LPOUT2_ALERTN", "GPOUT2_RESETN"; 241}; 242 243&gpiof { 244 gpio-line-names = "LPOUT3", "LPOUT3_ALERTN", "GPOUT3_RESETN", 245 "LPOUT4", "LPOUT4_ALERTN", "GPOUT4_RESETN", 246 "", "", 247 "", "", "", "", 248 "", "", "", ""; 249}; 250 251&gpiog { 252 gpio-line-names = "LPOUT5", "LPOUT5_ALERTN", "", "LPOUT5_RESETN", 253 "", "", "", "", 254 "", "", "", "", 255 "", "", "", ""; 256}; 257 258&gpioh { 259 gpio-line-names = "", "", "", "", 260 "", "", "", "", 261 "GPIO0_RESETN", "", "", "", 262 "", "", "", ""; 263}; 264 265&gpioi { 266 gpio-line-names = "", "", "", "", 267 "", "", "", "", 268 "HPDCM0_SLEEPN", "HPDCM1_SLEEPN", "GPIO1_RESETN", "", 269 "", "", "", ""; 270}; 271 272&gpioj { 273 gpio-line-names = "HSIN10", "HSIN11", "HSIN12", "HSIN13", 274 "HSIN14", "HSIN15", "", "", 275 "", "", "", "", 276 "", "RTD_RESETN", "", ""; 277}; 278 279&gpiok { 280 gpio-line-names = "", "", "HSIN0", "HSIN1", 281 "HSIN2", "HSIN3", "HSIN4", "HSIN5"; 282}; 283 284&gpioz { 285 gpio-line-names = "", "", "", "HSIN6", 286 "HSIN7", "HSIN8", "HSIN9", ""; 287}; 288 289&i2c2 { 290 pinctrl-names = "default"; 291 pinctrl-0 = <&i2c2_pins_a>; 292 pinctrl-1 = <&i2c2_sleep_pins_a>; 293 status = "okay"; 294 295 gpio0: gpio@20 { 296 compatible = "ti,tca6416"; 297 reg = <0x20>; 298 gpio-controller; 299 #gpio-cells = <2>; 300 gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS", 301 "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", 302 "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN9_BIAS", 303 "", "", "", ""; 304 }; 305 306 gpio1: gpio@21 { 307 compatible = "ti,tca6416"; 308 reg = <0x21>; 309 gpio-controller; 310 #gpio-cells = <2>; 311 gpio-line-names = "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BIAS", 312 "", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL", 313 "HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS", 314 "", "", "LSIN8_BIAS", "LSIN9_BIAS"; 315 }; 316}; 317 318&qspi { 319 pinctrl-names = "default", "sleep"; 320 pinctrl-0 = <&qspi_clk_pins_a 321 &qspi_bk1_pins_a 322 &qspi_cs1_pins_a>; 323 pinctrl-1 = <&qspi_clk_sleep_pins_a 324 &qspi_bk1_sleep_pins_a 325 &qspi_cs1_sleep_pins_a>; 326 status = "okay"; 327 328 flash@0 { 329 compatible = "jedec,spi-nor"; 330 reg = <0>; 331 spi-rx-bus-width = <4>; 332 spi-max-frequency = <104000000>; 333 #address-cells = <1>; 334 #size-cells = <1>; 335 }; 336}; 337 338&{qspi_bk1_pins_a/pins} { 339 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 340 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 341 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 342 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 343 /delete-property/ bias-disable; 344 bias-pull-up; 345}; 346 347&timers1 { 348 /delete-property/dmas; 349 /delete-property/dma-names; 350 status = "okay"; 351 352 hpdcm0_pwm: pwm { 353 pinctrl-names = "default", "sleep"; 354 pinctrl-0 = <&pwm1_pins_mecio1>; 355 pinctrl-1 = <&pwm1_sleep_pins_mecio1>; 356 status = "okay"; 357 }; 358}; 359 360&timers8 { 361 /delete-property/dmas; 362 /delete-property/dma-names; 363 status = "okay"; 364 365 hpdcm1_pwm: pwm { 366 pinctrl-names = "default", "sleep"; 367 pinctrl-0 = <&pwm8_pins_mecio1>; 368 pinctrl-1 = <&pwm8_sleep_pins_mecio1>; 369 status = "okay"; 370 }; 371}; 372 373&uart4 { 374 pinctrl-names = "default", "sleep", "idle"; 375 pinctrl-0 = <&uart4_pins_a>; 376 pinctrl-1 = <&uart4_sleep_pins_a>; 377 pinctrl-2 = <&uart4_idle_pins_a>; 378 /delete-property/dmas; 379 /delete-property/dma-names; 380 status = "okay"; 381}; 382 383&{uart4_pins_a/pins1} { 384 pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */ 385}; 386 387&{uart4_pins_a/pins2} { 388 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 389 /delete-property/ bias-disable; 390 bias-pull-up; 391}; 392 393&usbotg_hs { 394 dr_mode = "host"; 395 pinctrl-0 = <&usbotg_hs_pins_a>; 396 pinctrl-names = "default"; 397 phys = <&usbphyc_port1 0>; 398 phy-names = "usb2-phy"; 399 vbus-supply = <&v5v>; 400 status = "okay"; 401}; 402 403&usbphyc { 404 status = "okay"; 405}; 406 407&usbphyc_port0 { 408 phy-supply = <&v3v3>; 409}; 410 411&usbphyc_port1 { 412 phy-supply = <&v3v3>; 413}; 414 415&pinctrl { 416 adc12_pins_mecsbc: adc12-ain-mecsbc-0 { 417 pins { 418 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */ 419 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1_INP6 */ 420 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2_INP2 */ 421 <STM32_PINMUX('F', 14, ANALOG)>, /* ADC2_INP6 */ 422 <STM32_PINMUX('A', 0, ANALOG)>, /* ADC1_INP16 */ 423 <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */ 424 <STM32_PINMUX('A', 4, ANALOG)>, /* ADC1_INP18 */ 425 <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP19 */ 426 <STM32_PINMUX('A', 6, ANALOG)>, /* ADC1_INP3 */ 427 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */ 428 <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */ 429 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */ 430 <STM32_PINMUX('C', 3, ANALOG)>; /* ADC1_INP13 */ 431 }; 432 }; 433 434 pinctrl_hog_d_mecsbc: hog-d-0 { 435 pins { 436 pinmux = <STM32_PINMUX('D', 12, GPIO)>; /* STP_RESETn */ 437 bias-pull-up; 438 drive-push-pull; 439 slew-rate = <0>; 440 }; 441 }; 442 443 pwm1_pins_mecio1: pwm1-mecio1-0 { 444 pins { 445 pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */ 446 <STM32_PINMUX('A', 8, AF1)>; /* TIM1_CH2 */ 447 bias-pull-down; 448 drive-push-pull; 449 slew-rate = <0>; 450 }; 451 }; 452 453 pwm1_sleep_pins_mecio1: pwm1-sleep-mecio1-0 { 454 pins { 455 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* TIM1_CH1 */ 456 <STM32_PINMUX('A', 8, ANALOG)>; /* TIM1_CH2 */ 457 }; 458 }; 459 460 pwm8_pins_mecio1: pwm8-mecio1-0 { 461 pins { 462 pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */ 463 <STM32_PINMUX('I', 6, AF3)>; /* TIM8_CH2 */ 464 bias-pull-down; 465 drive-push-pull; 466 slew-rate = <0>; 467 }; 468 }; 469 470 pwm8_sleep_pins_mecio1: pwm8-sleep-mecio1-0 { 471 pins { 472 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */ 473 <STM32_PINMUX('I', 6, ANALOG)>; /* TIM8_CH2 */ 474 }; 475 }; 476 477 ethernet0_rgmii_pins_x: rgmii-0 { 478 pins1 { 479 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 480 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 481 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ 482 <STM32_PINMUX('B', 13, AF11)>, /* ETH_RGMII_TXD1 */ 483 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 484 <STM32_PINMUX('B', 8, AF11)>, /* ETH_RGMII_TXD3 */ 485 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 486 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 487 bias-disable; 488 drive-push-pull; 489 slew-rate = <3>; 490 }; 491 pins2 { 492 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 493 bias-disable; 494 drive-push-pull; 495 slew-rate = <0>; 496 }; 497 pins3 { 498 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 499 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 500 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 501 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ 502 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 503 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 504 bias-disable; 505 }; 506 }; 507 508 ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 { 509 pins1 { 510 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 511 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 512 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ 513 <STM32_PINMUX('B', 13, ANALOG)>, /* ETH_RGMII_TXD1 */ 514 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 515 <STM32_PINMUX('B', 8, ANALOG)>, /* ETH_RGMII_TXD3 */ 516 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 517 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 518 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 519 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 520 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 521 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 522 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ 523 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 524 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 525 }; 526 }; 527}; 528