| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | apple,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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| H A D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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| /linux/kernel/irq/ |
| H A D | cpuhotplug.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Generic cpu hotunplug interrupt migration code copied from the
19 /* For !GENERIC_IRQ_EFFECTIVE_AFF_MASK this looks at general affinity mask */
23 unsigned int cpu = smp_processor_id(); in irq_needs_fixup() local
28 * which do not implement effective affinity, but the architecture has in irq_needs_fixup()
29 * enabled the config switch. Use the general affinity mask instead. in irq_needs_fixup()
36 * CPU then it must contain at least one online CPU. The outgoing CPU in irq_needs_fixup()
39 if (cpumask_any_but(m, cpu) < nr_cpu_ids && in irq_needs_fixup()
45 pr_warn("Eff. affinity %*pbl of IRQ %u contains only offline CPUs after offlining CPU %u\n", in irq_needs_fixup()
46 cpumask_pr_args(m), d->irq, cpu); in irq_needs_fixup()
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| H A D | irqdesc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
7 * information is available in Documentation/core-api/genericirq.rst
23 * lockdep: we want to handle all irq_desc locks as a single lock-class:
33 * Set at least the boot cpu. We don't want to end up with in irq_affinity_setup()
57 if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, in alloc_masks()
59 return -ENOMEM; in alloc_masks()
62 if (!zalloc_cpumask_var_node(&desc->irq_common_data.effective_affinity, in alloc_masks()
64 free_cpumask_var(desc->irq_common_data.affinity); in alloc_masks()
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| H A D | chip.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 * This file contains the core interrupt handling code, for irq-chip based
8 * Documentation/core-api/genericirq.rst
37 * irq_set_chip - set the irq chip for an irq
43 int ret = -EINVAL; in irq_set_chip()
46 scoped_irqdesc->irq_data.chip = (struct irq_chip *)(chip ?: &no_irq_chip); in irq_set_chip()
57 * irq_set_irq_type - set the irq trigger type for an irq
59 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
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| H A D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
19 * Allocate a virq that can be used to send IPI to any CPU in dest mask.
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
48 * If the underlying implementation uses a single HW irq on in irq_reserve_ipi()
49 * all cpus then we only need a single Linux irq number for in irq_reserve_ipi()
59 * The IPI requires a separate HW irq on each CPU. We require in irq_reserve_ipi()
74 return -EINVAL; in irq_reserve_ipi()
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| /linux/drivers/iommu/ |
| H A D | hyperv-iommu.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V stub IOMMU driver.
18 #include <asm/cpu.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
42 struct irq_data *parent = data->parent_data; in hyperv_ir_set_affinity()
46 /* Return error If new irq affinity is out of ioapic_max_cpumask. */ in hyperv_ir_set_affinity()
48 return -EINVAL; in hyperv_ir_set_affinity()
50 ret = parent->chip->irq_set_affinity(parent, mask, force); in hyperv_ir_set_affinity()
60 .name = "HYPERV-IR",
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| /linux/tools/testing/selftests/bpf/benchs/ |
| H A D | run_bench_ringbufs.sh | 5 set -eufo pipefail
7 RUN_RB_BENCH="$RUN_BENCH -c1"
9 header "Single-producer, parallel producer"
10 for b in rb-libbpf rb-custom pb-libbpf pb-custom; do
14 header "Single-producer, parallel producer, sampled notification"
15 for b in rb-libbpf rb-custom pb-libbpf pb-custom; do
16 summarize $b "$($RUN_RB_BENCH --rb-sampled $b)"
19 header "Single-producer, back-to-back mode"
20 for b in rb-libbpf rb-custom pb-libbpf pb-custom; do
21 summarize $b "$($RUN_RB_BENCH --rb-b2b $b)"
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| /linux/Documentation/networking/ |
| H A D | scaling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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| H A D | pktgen.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
9 running, pktgen creates a thread for each CPU with affinity to that CPU.
13 On a dual CPU::
31 overload type of benchmarking, as this could hurt the normal use-case.
35 # ethtool -G ethX tx 1024
39 than the CPU's L1/L2 cache, 2) because it allows more queueing in the
44 ring-buffers for various performance reasons, and packets stalling
49 and the cleanup interval is affected by the ethtool --coalesce setting
50 of parameter "rx-usecs".
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| /linux/samples/pktgen/ |
| H A D | pktgen_sample06_numa_awared_queue_irq_affinity.sh | 5 # * bound devices queue's irq affinity to the threads, 1:1 mapping
14 # Required param: -i dev in $DEV
21 [ -z "$COUNT" ] && COUNT="20000000" # Zero means indefinitely
22 [ -z "$CLONE_SKB" ] && CLONE_SKB="0"
32 [ $THREADS -gt ${#irq_array[*]} -o $THREADS -gt ${#cpu_array[*]} ] && \
36 if [ -z "$DEST_IP" ]; then
37 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
39 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
40 if [ -n "$DEST_IP" ]; then
42 read -r DST_MIN DST_MAX <<< $(parse_addr${IP6} $DEST_IP)
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| /linux/include/linux/ |
| H A D | irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * Thanks. --rmk
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
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| /linux/Documentation/virt/hyperv/ |
| H A D | vpci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 …tps://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-deploying-devi…
23 and for GPUs. A similar mechanism for NICs is called SR-IOV
25 driver to interact directly with the hardware. See Hyper-V
26 public documentation here: `SR-IOV`_
28 .. _SR-IOV: https://learn.microsoft.com/en-us/windows-hardware/drivers/network/overview-of-single-r…
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| /linux/drivers/pci/msi/ |
| H A D | api.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
17 * pci_enable_msi() - Enable MSI interrupt mode on device
21 * allocate a single interrupt vector. On success, the allocated vector
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
46 * pin-assertion IRQ. This is the cleanup pair of pci_enable_msi().
53 if (!pci_msi_enabled() || !dev || !dev->msi_enabled) in pci_disable_msi()
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| /linux/arch/mips/sibyte/sb1250/ |
| H A D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
36 /* Store the CPU id (not the logical number) */
41 void sb1250_mask_irq(int cpu, int irq) in sb1250_mask_irq() argument
47 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + in sb1250_mask_irq()
50 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + in sb1250_mask_irq()
55 void sb1250_unmask_irq(int cpu, int irq) in sb1250_unmask_irq() argument
61 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + in sb1250_unmask_irq()
64 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + in sb1250_unmask_irq()
73 int i = 0, old_cpu, cpu, int_on; in sb1250_set_affinity() local
74 unsigned int irq = d->irq; in sb1250_set_affinity()
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| /linux/arch/powerpc/sysdev/xics/ |
| H A D | xics-common.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/cpu.h>
51 /* Find the server numbers for the boot cpu. */ in xics_update_irq_servers()
60 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); in xics_update_irq_servers()
69 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last in xics_update_irq_servers()
70 * entry fom this property for current boot cpu id and use it as in xics_update_irq_servers()
96 index = (1UL << xics_interrupt_server_size) - 1 - gserver; in xics_set_cpu_giq()
100 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", in xics_set_cpu_giq()
107 icp_ops->set_priority(LOWEST_PRIORITY); in xics_setup_cpu()
118 xics_ics->mask_unknown(xics_ics, vec); in xics_mask_unknown_vec()
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| /linux/tools/testing/selftests/kvm/ |
| H A D | rseq_test.c | 1 // SPDX-License-Identifier: GPL-2.0-only
33 * Any bug related to task migration is likely to be timing-dependent; perform
51 static int next_cpu(int cpu) in next_cpu() argument
54 * Advance to the next CPU, skipping those that weren't in the original in next_cpu()
55 * affinity set. Sadly, there is no CPU_SET_FOR_EACH, and cpu_set_t's in next_cpu()
62 cpu++; in next_cpu()
63 if (cpu > max_cpu) { in next_cpu()
64 cpu = min_cpu; in next_cpu()
65 TEST_ASSERT(CPU_ISSET(cpu, &possible_mask), in next_cpu()
66 "Min CPU = %d must always be usable", cpu); in next_cpu()
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| /linux/arch/arc/kernel/ |
| H A D | mcip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <asm/irqflags-arcv2.h>
26 static void mcip_update_gfrc_halt_mask(int cpu) in mcip_update_gfrc_halt_mask() argument
45 gfrc_halt_mask |= BIT(cpu); in mcip_update_gfrc_halt_mask()
51 static void mcip_update_debug_halt_mask(int cpu) in mcip_update_debug_halt_mask() argument
66 mcip_mask |= BIT(cpu); in mcip_update_debug_halt_mask()
71 * STATUS32[H]/actionpoint/breakpoint/self-halt in mcip_update_debug_halt_mask()
79 static void mcip_setup_per_cpu(int cpu) in mcip_setup_per_cpu() argument
85 smp_ipi_irq_setup(cpu, IPI_IRQ); in mcip_setup_per_cpu()
86 smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ); in mcip_setup_per_cpu()
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| /linux/tools/perf/util/ |
| H A D | evlist.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Parts came from builtin-{top,stat,record}.c, see those files for further
23 #include "affinity.h"
26 #include "bpf-event.h"
33 #include "util/bpf-filter.h"
37 #include "util/intel-tpebs.h"
45 #include "parse-events.h"
46 #include <subcmd/parse-options.h>
73 #define FD(e, x, y) (*(int *)xyarray__entry(e->core.fd, x, y))
74 #define SID(e, x, y) xyarray__entry(e->core.sample_id, x, y)
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| /linux/tools/perf/Documentation/ |
| H A D | perf-record.txt | 1 perf-record(1)
5 ----
6 perf-record - Run a command and record its profile into perf.data
9 --------
11 'perf record' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf record' [-e <EVENT> | --event=EVENT] [-a] \-- <command> [<options>]
15 -----------
17 from it, into perf.data - without displaying anything.
23 -------
27 -e::
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| /linux/arch/mips/sibyte/bcm1480/ |
| H A D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
37 /* Store the CPU id (not the logical number) */
42 void bcm1480_mask_irq(int cpu, int irq) in bcm1480_mask_irq() argument
51 irq -= BCM1480_NR_IRQS_HALF; in bcm1480_mask_irq()
53 …cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_sp… in bcm1480_mask_irq()
55 …____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_sp… in bcm1480_mask_irq()
59 void bcm1480_unmask_irq(int cpu, int irq) in bcm1480_unmask_irq() argument
68 irq -= BCM1480_NR_IRQS_HALF; in bcm1480_unmask_irq()
70 …cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_sp… in bcm1480_unmask_irq()
72 …____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_sp… in bcm1480_unmask_irq()
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| /linux/tools/testing/selftests/seccomp/ |
| H A D | seccomp_benchmark.c | 39 i = finish.tv_sec - start.tv_sec; in timing()
41 i += finish.tv_nsec - start.tv_nsec; in timing()
43 ksft_print_msg("%lu.%09lu - %lu.%09lu = %llu (%.1fs)\n", in timing()
71 i = finish.tv_sec - start.tv_sec; in calibrate()
73 i += finish.tv_nsec - start.tv_nsec; in calibrate()
140 /* Pin to a single CPU so the benchmark won't bounce around the system. */
141 void affinity(void) in affinity() function
143 long cpu; in affinity() local
150 * choose the highest CPU instea in affinity()
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| /linux/Documentation/networking/dsa/ |
| H A D | configuration.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 .. _dsa-config-showcases:
13 -----------------------
18 *single port*
33 interface. The CPU port is the switch port connected to an Ethernet MAC chip.
42 - when a DSA user interface is brought up, the conduit interface is
44 - when the conduit interface is brought down, all DSA user interfaces are
70 *single port*
71 * lan1: 192.0.2.1/30 (192.0.2.0 - 192.0.2.3)
72 * lan2: 192.0.2.5/30 (192.0.2.4 - 192.0.2.7)
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | l1tf.rst | 1 L1TF - L1 Terminal Fault
10 -------------------
15 - Processors from AMD, Centaur and other non Intel vendors
17 - Older processor models, where the CPU family is < 6
19 - A range of Intel ATOM processors (Cedarview, Cloverview, Lincroft,
22 - The Intel XEON PHI family
24 - Intel processors which have the ARCH_CAP_RDCL_NO bit set in the
25 IA32_ARCH_CAPABILITIES MSR. If the bit is set the CPU is not affected
33 ------------
38 CVE-2018-3615 L1 Terminal Fault SGX related aspects
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| /linux/arch/mips/cavium-octeon/ |
| H A D | octeon-irq.c | 6 * Copyright (C) 2004-2016 Cavium, Inc.
21 #include <asm/octeon/cvmx-ciu2-defs.h>
22 #include <asm/octeon/cvmx-ciu3-defs.h>
82 int current_cpu; /* Next CPU expected to take this irq */
105 return -ENOMEM; in octeon_irq_set_ciu_mapping()
109 cd->line = line; in octeon_irq_set_ciu_mapping()
110 cd->bit = bit; in octeon_irq_set_ciu_mapping()
111 cd->gpio_line = gpio_line; in octeon_irq_set_ciu_mapping()
135 return -EINVAL; in octeon_irq_force_ciu_mapping()
143 static int octeon_coreid_for_cpu(int cpu) in octeon_coreid_for_cpu() argument
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