1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <asm/irqflags-arcv2.h>
26 static void mcip_update_gfrc_halt_mask(int cpu)  in mcip_update_gfrc_halt_mask()  argument
45 	gfrc_halt_mask |= BIT(cpu);  in mcip_update_gfrc_halt_mask()
51 static void mcip_update_debug_halt_mask(int cpu)  in mcip_update_debug_halt_mask()  argument
66 	mcip_mask |= BIT(cpu);  in mcip_update_debug_halt_mask()
71 	 * STATUS32[H]/actionpoint/breakpoint/self-halt  in mcip_update_debug_halt_mask()
79 static void mcip_setup_per_cpu(int cpu)  in mcip_setup_per_cpu()  argument
85 	smp_ipi_irq_setup(cpu, IPI_IRQ);  in mcip_setup_per_cpu()
86 	smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);  in mcip_setup_per_cpu()
88 	/* Update GFRC halt mask as new CPU came online */  in mcip_setup_per_cpu()
90 		mcip_update_gfrc_halt_mask(cpu);  in mcip_setup_per_cpu()
92 	/* Update MCIP debug mask as new CPU came online */  in mcip_setup_per_cpu()
94 		mcip_update_debug_halt_mask(cpu);  in mcip_setup_per_cpu()
97 static void mcip_ipi_send(int cpu)  in mcip_ipi_send()  argument
103 	if (unlikely(cpu == raw_smp_processor_id())) {  in mcip_ipi_send()
116 	__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);  in mcip_ipi_send()
119 		__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);  in mcip_ipi_send()
126 	unsigned int cpu, c;  in mcip_ipi_clear()  local
139 	cpu = read_aux_reg(ARC_REG_MCIP_READBACK);	/* 1,2,4,8... */  in mcip_ipi_clear()
144 	 * "vectored" (multiple bits sets) as opposed to typical single bit  in mcip_ipi_clear()
147 		c = __ffs(cpu);			/* 0,1,2,3 */  in mcip_ipi_clear()
149 		cpu &= ~(1U << c);  in mcip_ipi_clear()
150 	} while (cpu);  in mcip_ipi_clear()
184  *  -dynamic routing (IRQ affinity)
185  *  -load balancing (Round Robin interrupt distribution)
186  *  -1:N distribution
232 	idu_irq_mask_raw(data->hwirq);  in idu_irq_mask()
240 	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);  in idu_irq_unmask()
249 	__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);  in idu_irq_ack()
258 	__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);  in idu_irq_mask_ack()
259 	__mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);  in idu_irq_mask_ack()
272 	/* errout if no online cpu per @cpumask */  in idu_irq_set_affinity()
274 		return -EINVAL;  in idu_irq_set_affinity()
279 	idu_set_dest(data->hwirq, destination_bits);  in idu_irq_set_affinity()
286 	idu_set_mode(data->hwirq, false, 0, true, distribution_mode);  in idu_irq_set_affinity()
302 		return -EINVAL;  in idu_irq_set_type()
306 	idu_set_mode(data->hwirq, true,  in idu_irq_set_type()
320 	 * The affinity of common interrupts in IDU must be set manually since  in idu_irq_enable()
324 	 *      interrupt controllers does not support setting of the affinity  in idu_irq_enable()
350 	irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;  in idu_cascade_isr()
369  * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
371  * [24+C, N]: Not statically assigned, private-per-core
397 	/* Parent interrupts (core-intc) are already mapped */  in idu_of_init()
418 IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);