Lines Matching +full:single +full:- +full:cpu +full:- +full:affinity
6 * Copyright (C) 2004-2016 Cavium, Inc.
21 #include <asm/octeon/cvmx-ciu2-defs.h>
22 #include <asm/octeon/cvmx-ciu3-defs.h>
82 int current_cpu; /* Next CPU expected to take this irq */
105 return -ENOMEM; in octeon_irq_set_ciu_mapping()
109 cd->line = line; in octeon_irq_set_ciu_mapping()
110 cd->bit = bit; in octeon_irq_set_ciu_mapping()
111 cd->gpio_line = gpio_line; in octeon_irq_set_ciu_mapping()
135 return -EINVAL; in octeon_irq_force_ciu_mapping()
143 static int octeon_coreid_for_cpu(int cpu) in octeon_coreid_for_cpu() argument
146 return cpu_logical_map(cpu); in octeon_coreid_for_cpu()
164 unsigned int bit = cd->bit; in octeon_irq_core_ack()
186 set_c0_status(0x100 << cd->bit); in octeon_irq_core_eoi()
193 unsigned int mask = 0x100 << cd->bit; in octeon_irq_core_set_enable_local()
198 if (cd->desired_en) in octeon_irq_core_set_enable_local()
208 cd->desired_en = false; in octeon_irq_core_disable()
214 cd->desired_en = true; in octeon_irq_core_enable()
221 mutex_lock(&cd->core_irq_mutex); in octeon_irq_core_bus_lock()
228 if (cd->desired_en != cd->current_en) { in octeon_irq_core_bus_sync_unlock()
231 cd->current_en = cd->desired_en; in octeon_irq_core_bus_sync_unlock()
234 mutex_unlock(&cd->core_irq_mutex); in octeon_irq_core_bus_sync_unlock()
259 cd->current_en = false; in octeon_irq_init_core()
260 cd->desired_en = false; in octeon_irq_init_core()
261 cd->bit = i; in octeon_irq_init_core()
262 mutex_init(&cd->core_irq_mutex); in octeon_irq_init_core()
275 int cpu; in next_cpu_for_irq() local
281 cpu = cd->current_cpu; in next_cpu_for_irq()
283 cpu = cpumask_next(cpu, mask); in next_cpu_for_irq()
284 if (cpu >= nr_cpu_ids) { in next_cpu_for_irq()
285 cpu = -1; in next_cpu_for_irq()
287 } else if (cpumask_test_cpu(cpu, cpu_online_mask)) { in next_cpu_for_irq()
292 cpu = cpumask_first(mask); in next_cpu_for_irq()
294 cpu = smp_processor_id(); in next_cpu_for_irq()
296 cd->current_cpu = cpu; in next_cpu_for_irq()
297 return cpu; in next_cpu_for_irq()
305 int cpu = next_cpu_for_irq(data); in octeon_irq_ciu_enable() local
306 int coreid = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_enable()
310 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); in octeon_irq_ciu_enable()
315 if (cd->line == 0) { in octeon_irq_ciu_enable()
316 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); in octeon_irq_ciu_enable()
317 __set_bit(cd->bit, pen); in octeon_irq_ciu_enable()
325 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); in octeon_irq_ciu_enable()
326 __set_bit(cd->bit, pen); in octeon_irq_ciu_enable()
347 if (cd->line == 0) { in octeon_irq_ciu_enable_local()
349 __set_bit(cd->bit, pen); in octeon_irq_ciu_enable_local()
358 __set_bit(cd->bit, pen); in octeon_irq_ciu_enable_local()
379 if (cd->line == 0) { in octeon_irq_ciu_disable_local()
381 __clear_bit(cd->bit, pen); in octeon_irq_ciu_disable_local()
390 __clear_bit(cd->bit, pen); in octeon_irq_ciu_disable_local()
405 int cpu; in octeon_irq_ciu_disable_all() local
411 for_each_online_cpu(cpu) { in octeon_irq_ciu_disable_all()
412 int coreid = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_disable_all()
413 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); in octeon_irq_ciu_disable_all()
414 if (cd->line == 0) in octeon_irq_ciu_disable_all()
415 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); in octeon_irq_ciu_disable_all()
417 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); in octeon_irq_ciu_disable_all()
420 __clear_bit(cd->bit, pen); in octeon_irq_ciu_disable_all()
426 if (cd->line == 0) in octeon_irq_ciu_disable_all()
438 int cpu; in octeon_irq_ciu_enable_all() local
444 for_each_online_cpu(cpu) { in octeon_irq_ciu_enable_all()
445 int coreid = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_enable_all()
446 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); in octeon_irq_ciu_enable_all()
447 if (cd->line == 0) in octeon_irq_ciu_enable_all()
448 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); in octeon_irq_ciu_enable_all()
450 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); in octeon_irq_ciu_enable_all()
453 __set_bit(cd->bit, pen); in octeon_irq_ciu_enable_all()
459 if (cd->line == 0) in octeon_irq_ciu_enable_all()
468 * Enable the irq on the next core in the affinity set for chips that
474 int cpu = next_cpu_for_irq(data); in octeon_irq_ciu_enable_v2() local
478 mask = 1ull << (cd->bit); in octeon_irq_ciu_enable_v2()
484 if (cd->line == 0) { in octeon_irq_ciu_enable_v2()
485 int index = octeon_coreid_for_cpu(cpu) * 2; in octeon_irq_ciu_enable_v2()
486 set_bit(cd->bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); in octeon_irq_ciu_enable_v2()
489 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; in octeon_irq_ciu_enable_v2()
490 set_bit(cd->bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); in octeon_irq_ciu_enable_v2()
501 int cpu = next_cpu_for_irq(data); in octeon_irq_ciu_enable_sum2() local
502 int index = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_enable_sum2()
506 mask = 1ull << (cd->bit); in octeon_irq_ciu_enable_sum2()
517 int cpu = next_cpu_for_irq(data); in octeon_irq_ciu_disable_local_sum2() local
518 int index = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_disable_local_sum2()
522 mask = 1ull << (cd->bit); in octeon_irq_ciu_disable_local_sum2()
530 int cpu = next_cpu_for_irq(data); in octeon_irq_ciu_ack_sum2() local
531 int index = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_ack_sum2()
535 mask = 1ull << (cd->bit); in octeon_irq_ciu_ack_sum2()
542 int cpu; in octeon_irq_ciu_disable_all_sum2() local
547 mask = 1ull << (cd->bit); in octeon_irq_ciu_disable_all_sum2()
549 for_each_online_cpu(cpu) { in octeon_irq_ciu_disable_all_sum2()
550 int coreid = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_disable_all_sum2()
557 * Enable the irq on the current CPU for chips that
566 mask = 1ull << (cd->bit); in octeon_irq_ciu_enable_local_v2()
568 if (cd->line == 0) { in octeon_irq_ciu_enable_local_v2()
570 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror)); in octeon_irq_ciu_enable_local_v2()
574 set_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror)); in octeon_irq_ciu_enable_local_v2()
585 mask = 1ull << (cd->bit); in octeon_irq_ciu_disable_local_v2()
587 if (cd->line == 0) { in octeon_irq_ciu_disable_local_v2()
589 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu0_en_mirror)); in octeon_irq_ciu_disable_local_v2()
593 clear_bit(cd->bit, this_cpu_ptr(&octeon_irq_ciu1_en_mirror)); in octeon_irq_ciu_disable_local_v2()
607 mask = 1ull << (cd->bit); in octeon_irq_ciu_ack()
609 if (cd->line == 0) { in octeon_irq_ciu_ack()
623 int cpu; in octeon_irq_ciu_disable_all_v2() local
628 mask = 1ull << (cd->bit); in octeon_irq_ciu_disable_all_v2()
630 if (cd->line == 0) { in octeon_irq_ciu_disable_all_v2()
631 for_each_online_cpu(cpu) { in octeon_irq_ciu_disable_all_v2()
632 int index = octeon_coreid_for_cpu(cpu) * 2; in octeon_irq_ciu_disable_all_v2()
633 clear_bit(cd->bit, in octeon_irq_ciu_disable_all_v2()
634 &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); in octeon_irq_ciu_disable_all_v2()
638 for_each_online_cpu(cpu) { in octeon_irq_ciu_disable_all_v2()
639 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; in octeon_irq_ciu_disable_all_v2()
640 clear_bit(cd->bit, in octeon_irq_ciu_disable_all_v2()
641 &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); in octeon_irq_ciu_disable_all_v2()
653 int cpu; in octeon_irq_ciu_enable_all_v2() local
658 mask = 1ull << (cd->bit); in octeon_irq_ciu_enable_all_v2()
660 if (cd->line == 0) { in octeon_irq_ciu_enable_all_v2()
661 for_each_online_cpu(cpu) { in octeon_irq_ciu_enable_all_v2()
662 int index = octeon_coreid_for_cpu(cpu) * 2; in octeon_irq_ciu_enable_all_v2()
663 set_bit(cd->bit, in octeon_irq_ciu_enable_all_v2()
664 &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); in octeon_irq_ciu_enable_all_v2()
668 for_each_online_cpu(cpu) { in octeon_irq_ciu_enable_all_v2()
669 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; in octeon_irq_ciu_enable_all_v2()
670 set_bit(cd->bit, in octeon_irq_ciu_enable_all_v2()
671 &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); in octeon_irq_ciu_enable_all_v2()
706 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), cfg.u64); in octeon_irq_gpio_setup()
739 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio_v2()
749 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu_disable_gpio()
760 mask = 1ull << (cd->gpio_line); in octeon_irq_ciu_gpio_ack()
769 int cpu = smp_processor_id(); in octeon_irq_cpu_offline_ciu() local
773 if (!cpumask_test_cpu(cpu, mask)) in octeon_irq_cpu_offline_ciu()
778 * It has multi CPU affinity, just remove this CPU in octeon_irq_cpu_offline_ciu()
779 * from the affinity set. in octeon_irq_cpu_offline_ciu()
782 cpumask_clear_cpu(cpu, &new_affinity); in octeon_irq_cpu_offline_ciu()
784 /* Otherwise, put it on lowest numbered online CPU. */ in octeon_irq_cpu_offline_ciu()
794 int cpu; in octeon_irq_ciu_set_affinity() local
804 * For non-v2 CIU, we will allow only single CPU affinity. in octeon_irq_ciu_set_affinity()
809 return -EINVAL; in octeon_irq_ciu_set_affinity()
815 for_each_online_cpu(cpu) { in octeon_irq_ciu_set_affinity()
816 int coreid = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_set_affinity()
818 lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); in octeon_irq_ciu_set_affinity()
821 if (cd->line == 0) in octeon_irq_ciu_set_affinity()
822 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); in octeon_irq_ciu_set_affinity()
824 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); in octeon_irq_ciu_set_affinity()
826 if (cpumask_test_cpu(cpu, dest) && enable_one) { in octeon_irq_ciu_set_affinity()
828 __set_bit(cd->bit, pen); in octeon_irq_ciu_set_affinity()
830 __clear_bit(cd->bit, pen); in octeon_irq_ciu_set_affinity()
838 if (cd->line == 0) in octeon_irq_ciu_set_affinity()
849 * Set affinity for the irq for chips that have the EN*_W1{S,C}
856 int cpu; in octeon_irq_ciu_set_affinity_v2() local
865 mask = 1ull << cd->bit; in octeon_irq_ciu_set_affinity_v2()
867 if (cd->line == 0) { in octeon_irq_ciu_set_affinity_v2()
868 for_each_online_cpu(cpu) { in octeon_irq_ciu_set_affinity_v2()
869 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); in octeon_irq_ciu_set_affinity_v2()
870 int index = octeon_coreid_for_cpu(cpu) * 2; in octeon_irq_ciu_set_affinity_v2()
871 if (cpumask_test_cpu(cpu, dest) && enable_one) { in octeon_irq_ciu_set_affinity_v2()
873 set_bit(cd->bit, pen); in octeon_irq_ciu_set_affinity_v2()
876 clear_bit(cd->bit, pen); in octeon_irq_ciu_set_affinity_v2()
881 for_each_online_cpu(cpu) { in octeon_irq_ciu_set_affinity_v2()
882 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); in octeon_irq_ciu_set_affinity_v2()
883 int index = octeon_coreid_for_cpu(cpu) * 2 + 1; in octeon_irq_ciu_set_affinity_v2()
884 if (cpumask_test_cpu(cpu, dest) && enable_one) { in octeon_irq_ciu_set_affinity_v2()
886 set_bit(cd->bit, pen); in octeon_irq_ciu_set_affinity_v2()
889 clear_bit(cd->bit, pen); in octeon_irq_ciu_set_affinity_v2()
901 int cpu; in octeon_irq_ciu_set_affinity_sum2() local
910 mask = 1ull << cd->bit; in octeon_irq_ciu_set_affinity_sum2()
912 for_each_online_cpu(cpu) { in octeon_irq_ciu_set_affinity_sum2()
913 int index = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu_set_affinity_sum2()
915 if (cpumask_test_cpu(cpu, dest) && enable_one) { in octeon_irq_ciu_set_affinity_sum2()
928 /* ack any pending edge-irq at startup, so there is in edge_startup()
931 data->chip->irq_ack(data); in edge_startup()
932 data->chip->irq_enable(data); in edge_startup()
1017 /* The mbox versions don't do any affinity or round-robin. */
1019 .name = "CIU-M",
1031 .name = "CIU-M",
1043 .name = "CIU-GPIO",
1058 .name = "CIU-GPIO",
1073 * Watchdog interrupts are special. They are associated with a single
1074 * core, so we hardwire the affinity to that core.
1080 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ in octeon_irq_ciu_wd_enable()
1081 int cpu = octeon_cpu_for_coreid(coreid); in octeon_irq_ciu_wd_enable() local
1082 raw_spinlock_t *lock = &per_cpu(octeon_irq_ciu_spinlock, cpu); in octeon_irq_ciu_wd_enable()
1085 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); in octeon_irq_ciu_wd_enable()
1097 * Watchdog interrupts are special. They are associated with a single
1098 * core, so we hardwire the affinity to that core.
1102 int coreid = data->irq - OCTEON_IRQ_WDOG0; in octeon_irq_ciu1_wd_enable_v2()
1103 int cpu = octeon_cpu_for_coreid(coreid); in octeon_irq_ciu1_wd_enable_v2() local
1105 set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); in octeon_irq_ciu1_wd_enable_v2()
1111 .name = "CIU-W",
1119 .name = "CIU-W",
1168 return -EINVAL; in octeon_irq_gpio_xlat()
1171 return -EINVAL; in octeon_irq_gpio_xlat()
1175 return -EINVAL; in octeon_irq_gpio_xlat()
1213 struct octeon_irq_ciu_domain_data *dd = d->host_data; in octeon_irq_ciu_xlat()
1218 if (ciu >= dd->num_sum || bit > 63) in octeon_irq_ciu_xlat()
1219 return -EINVAL; in octeon_irq_ciu_xlat()
1237 struct octeon_irq_ciu_domain_data *dd = d->host_data; in octeon_irq_ciu_map()
1239 if (line >= dd->num_sum || octeon_irq_ciu_to_irq[line][bit] != 0) in octeon_irq_ciu_map()
1240 return -EINVAL; in octeon_irq_ciu_map()
1267 struct octeon_irq_gpio_domain_data *gpiod = d->host_data; in octeon_irq_gpio_map()
1271 line = (hw + gpiod->base_hwirq) >> 6; in octeon_irq_gpio_map()
1272 bit = (hw + gpiod->base_hwirq) & 63; in octeon_irq_gpio_map()
1275 return -EINVAL; in octeon_irq_gpio_map()
1306 int bit = fls64(ciu_sum) - 1; in octeon_irq_ip2_ciu()
1323 int bit = fls64(ciu_sum) - 1; in octeon_irq_ip3_ciu()
1342 int bit = fls64(ciu_sum) - 1; in octeon_irq_ip4_ciu()
1467 return -ENOMEM; in octeon_irq_init_ciu()
1477 dd->num_sum = 3; in octeon_irq_init_ciu()
1481 dd->num_sum = 2; in octeon_irq_init_ciu()
1518 r = irq_alloc_desc_at(OCTEON_IRQ_MBOX0, -1); in octeon_irq_init_ciu()
1527 r = irq_alloc_desc_at(OCTEON_IRQ_MBOX1, -1); in octeon_irq_init_ciu()
1569 r = irq_alloc_descs(OCTEON_IRQ_WDOG0, OCTEON_IRQ_WDOG0, 16, -1); in octeon_irq_init_ciu()
1603 r = of_property_read_u32(parent, "#interrupt-cells", &interrupt_cells); in octeon_irq_init_gpio()
1631 pr_warn("Bad \"#interrupt-cells\" property: %u\n", in octeon_irq_init_gpio()
1633 return -EINVAL; in octeon_irq_init_gpio()
1639 gpiod->base_hwirq = base_hwirq; in octeon_irq_init_gpio()
1644 return -ENOMEM; in octeon_irq_init_gpio()
1656 * Watchdog interrupts are special. They are associated with a single
1657 * core, so we hardwire the affinity to that core.
1663 int coreid = data->irq - OCTEON_IRQ_WDOG0; in octeon_irq_ciu2_wd_enable()
1667 mask = 1ull << (cd->bit); in octeon_irq_ciu2_wd_enable()
1670 (0x1000ull * cd->line); in octeon_irq_ciu2_wd_enable()
1679 int cpu = next_cpu_for_irq(data); in octeon_irq_ciu2_enable() local
1680 int coreid = octeon_coreid_for_cpu(cpu); in octeon_irq_ciu2_enable()
1684 mask = 1ull << (cd->bit); in octeon_irq_ciu2_enable()
1687 (0x1000ull * cd->line); in octeon_irq_ciu2_enable()
1699 mask = 1ull << (cd->bit); in octeon_irq_ciu2_enable_local()
1702 (0x1000ull * cd->line); in octeon_irq_ciu2_enable_local()
1715 mask = 1ull << (cd->bit); in octeon_irq_ciu2_disable_local()
1718 (0x1000ull * cd->line); in octeon_irq_ciu2_disable_local()
1731 mask = 1ull << (cd->bit); in octeon_irq_ciu2_ack()
1733 en_addr = CVMX_CIU2_RAW_PPX_IP2_WRKQ(coreid) + (0x1000ull * cd->line); in octeon_irq_ciu2_ack()
1740 int cpu; in octeon_irq_ciu2_disable_all() local
1745 mask = 1ull << (cd->bit); in octeon_irq_ciu2_disable_all()
1747 for_each_online_cpu(cpu) { in octeon_irq_ciu2_disable_all()
1749 octeon_coreid_for_cpu(cpu)) + (0x1000ull * cd->line); in octeon_irq_ciu2_disable_all()
1756 int cpu; in octeon_irq_ciu2_mbox_enable_all() local
1759 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); in octeon_irq_ciu2_mbox_enable_all()
1761 for_each_online_cpu(cpu) { in octeon_irq_ciu2_mbox_enable_all()
1763 octeon_coreid_for_cpu(cpu)); in octeon_irq_ciu2_mbox_enable_all()
1770 int cpu; in octeon_irq_ciu2_mbox_disable_all() local
1773 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); in octeon_irq_ciu2_mbox_disable_all()
1775 for_each_online_cpu(cpu) { in octeon_irq_ciu2_mbox_disable_all()
1777 octeon_coreid_for_cpu(cpu)); in octeon_irq_ciu2_mbox_disable_all()
1788 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); in octeon_irq_ciu2_mbox_enable_local()
1799 mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); in octeon_irq_ciu2_mbox_disable_local()
1808 int cpu; in octeon_irq_ciu2_set_affinity() local
1817 mask = 1ull << cd->bit; in octeon_irq_ciu2_set_affinity()
1819 for_each_online_cpu(cpu) { in octeon_irq_ciu2_set_affinity()
1821 if (cpumask_test_cpu(cpu, dest) && enable_one) { in octeon_irq_ciu2_set_affinity()
1824 octeon_coreid_for_cpu(cpu)) + in octeon_irq_ciu2_set_affinity()
1825 (0x1000ull * cd->line); in octeon_irq_ciu2_set_affinity()
1828 octeon_coreid_for_cpu(cpu)) + in octeon_irq_ciu2_set_affinity()
1829 (0x1000ull * cd->line); in octeon_irq_ciu2_set_affinity()
1850 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd->gpio_line), 0); in octeon_irq_ciu2_disable_gpio()
1856 .name = "CIU2-E",
1868 .name = "CIU2-E",
1881 .name = "CIU2-M",
1893 .name = "CIU2-W",
1901 .name = "CIU-GPIO",
1973 return -EINVAL; in octeon_irq_ciu2_map()
2006 line = fls64(sum) - 1; in octeon_irq_ciu2()
2013 bit = fls64(src) - 1; in octeon_irq_ciu2()
2043 line = fls64(sum) - 1; in octeon_irq_ciu2_mbox()
2147 struct octeon_irq_cib_host_data *host_data = cd->host_data; in octeon_irq_cib_enable()
2149 raw_spin_lock_irqsave(&host_data->lock, flags); in octeon_irq_cib_enable()
2150 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_enable()
2151 en |= 1ull << cd->bit; in octeon_irq_cib_enable()
2152 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_enable()
2153 raw_spin_unlock_irqrestore(&host_data->lock, flags); in octeon_irq_cib_enable()
2161 struct octeon_irq_cib_host_data *host_data = cd->host_data; in octeon_irq_cib_disable()
2163 raw_spin_lock_irqsave(&host_data->lock, flags); in octeon_irq_cib_disable()
2164 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_disable()
2165 en &= ~(1ull << cd->bit); in octeon_irq_cib_disable()
2166 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_disable()
2167 raw_spin_unlock_irqrestore(&host_data->lock, flags); in octeon_irq_cib_disable()
2206 return -EINVAL; in octeon_irq_cib_xlat()
2217 struct octeon_irq_cib_host_data *host_data = d->host_data; in octeon_irq_cib_map()
2220 if (hw >= host_data->max_bits) { in octeon_irq_cib_map()
2222 irq_domain_get_of_node(d)->name, (unsigned)hw); in octeon_irq_cib_map()
2223 return -EINVAL; in octeon_irq_cib_map()
2228 return -ENOMEM; in octeon_irq_cib_map()
2230 cd->host_data = host_data; in octeon_irq_cib_map()
2231 cd->bit = hw; in octeon_irq_cib_map()
2254 struct octeon_irq_cib_host_data *host_data = cib_domain->host_data; in octeon_irq_cib_handler()
2256 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_handler()
2257 raw = cvmx_read_csr(host_data->raw_reg); in octeon_irq_cib_handler()
2261 for (i = 0; i < host_data->max_bits; i++) { in octeon_irq_cib_handler()
2269 i, host_data->raw_reg); in octeon_irq_cib_handler()
2270 raw_spin_lock_irqsave(&host_data->lock, flags); in octeon_irq_cib_handler()
2271 en = cvmx_read_csr(host_data->en_reg); in octeon_irq_cib_handler()
2273 cvmx_write_csr(host_data->en_reg, en); in octeon_irq_cib_handler()
2274 cvmx_write_csr(host_data->raw_reg, 1ull << i); in octeon_irq_cib_handler()
2275 raw_spin_unlock_irqrestore(&host_data->lock, flags); in octeon_irq_cib_handler()
2282 cvmx_write_csr(host_data->raw_reg, 1ull << i); in octeon_irq_cib_handler()
2304 return -EINVAL; in octeon_irq_init_cib()
2309 return -ENOMEM; in octeon_irq_init_cib()
2310 raw_spin_lock_init(&host_data->lock); in octeon_irq_init_cib()
2317 host_data->raw_reg = (u64)phys_to_virt(res.start); in octeon_irq_init_cib()
2324 host_data->en_reg = (u64)phys_to_virt(res.start); in octeon_irq_init_cib()
2326 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); in octeon_irq_init_cib()
2328 pr_err("ERROR: Couldn't read cavium,max-bits from %pOFn\n", in octeon_irq_init_cib()
2332 host_data->max_bits = val; in octeon_irq_init_cib()
2335 host_data->max_bits, in octeon_irq_init_cib()
2340 return -ENOMEM; in octeon_irq_init_cib()
2343 cvmx_write_csr(host_data->en_reg, 0); /* disable all IRQs */ in octeon_irq_init_cib()
2344 cvmx_write_csr(host_data->raw_reg, ~0); /* ack any outstanding */ in octeon_irq_init_cib()
2353 host_data->raw_reg, host_data->max_bits); in octeon_irq_init_cib()
2364 struct octeon_ciu3_info *ciu3_info = d->host_data; in octeon_irq_ciu3_xlat()
2369 return -EINVAL; in octeon_irq_ciu3_xlat()
2374 return -EINVAL; in octeon_irq_ciu3_xlat()
2379 return -EINVAL; in octeon_irq_ciu3_xlat()
2384 isc.u64 = cvmx_read_csr(ciu3_info->ciu3_addr + CIU3_ISC_CTL(hwirq)); in octeon_irq_ciu3_xlat()
2386 return -EINVAL; in octeon_irq_ciu3_xlat()
2397 return -EINVAL; in octeon_irq_ciu3_xlat()
2407 int cpu; in octeon_irq_ciu3_enable() local
2414 cpu = next_cpu_for_irq(data); in octeon_irq_ciu3_enable()
2420 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); in octeon_irq_ciu3_enable()
2422 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn); in octeon_irq_ciu3_enable()
2425 isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu); in octeon_irq_ciu3_enable()
2442 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn); in octeon_irq_ciu3_disable()
2443 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); in octeon_irq_ciu3_disable()
2456 * We use a single irq_chip, so we have to do nothing to ack a in octeon_irq_ciu3_ack()
2467 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn); in octeon_irq_ciu3_ack()
2483 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn); in octeon_irq_ciu3_mask()
2501 * We use a single irq_chip, so only ack an edge (!level) in octeon_irq_ciu3_mask_ack()
2507 isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn); in octeon_irq_ciu3_mask_ack()
2519 int cpu; in octeon_irq_ciu3_set_affinity() local
2523 if (!cpumask_subset(dest, cpumask_of_node(cd->ciu_node))) in octeon_irq_ciu3_set_affinity()
2524 return -EINVAL; in octeon_irq_ciu3_set_affinity()
2530 cpu = cpumask_first(dest); in octeon_irq_ciu3_set_affinity()
2531 if (cpu >= nr_cpu_ids) in octeon_irq_ciu3_set_affinity()
2532 cpu = smp_processor_id(); in octeon_irq_ciu3_set_affinity()
2533 cd->current_cpu = cpu; in octeon_irq_ciu3_set_affinity()
2537 cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64); in octeon_irq_ciu3_set_affinity()
2539 isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn); in octeon_irq_ciu3_set_affinity()
2542 isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu); in octeon_irq_ciu3_set_affinity()
2569 struct octeon_ciu3_info *ciu3_info = d->host_data; in octeon_irq_ciu3_mapx()
2571 ciu3_info->node); in octeon_irq_ciu3_mapx()
2573 return -ENOMEM; in octeon_irq_ciu3_mapx()
2574 cd->intsn = hw; in octeon_irq_ciu3_mapx()
2575 cd->current_cpu = -1; in octeon_irq_ciu3_mapx()
2576 cd->ciu3_addr = ciu3_info->ciu3_addr; in octeon_irq_ciu3_mapx()
2577 cd->ciu_node = ciu3_info->node; in octeon_irq_ciu3_mapx()
2603 ciu3_addr = ciu3_info->ciu3_addr; in octeon_irq_ciu3_ip2()
2615 domain = ciu3_info->domain[block]; in octeon_irq_ciu3_ip2()
2616 if (ciu3_info->intsn2hw[block]) in octeon_irq_ciu3_ip2()
2617 hw = ciu3_info->intsn2hw[block](domain, intsn); in octeon_irq_ciu3_ip2()
2655 static unsigned int octeon_irq_ciu3_mbox_intsn_for_cpu(int cpu, unsigned int mbox) in octeon_irq_ciu3_mbox_intsn_for_cpu() argument
2657 int local_core = octeon_coreid_for_cpu(cpu) & 0x3f; in octeon_irq_ciu3_mbox_intsn_for_cpu()
2670 ciu3_addr = ciu3_info->ciu3_addr; in octeon_irq_ciu3_mbox()
2676 int mbox = intsn - octeon_irq_ciu3_base_mbox_intsn(core); in octeon_irq_ciu3_mbox()
2695 void octeon_ciu3_mbox_send(int cpu, unsigned int mbox) in octeon_ciu3_mbox_send() argument
2705 intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox); in octeon_ciu3_mbox_send()
2706 ciu3_info = per_cpu(octeon_ciu3_info, cpu); in octeon_ciu3_mbox_send()
2707 isc_w1s_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1S(intsn); in octeon_ciu3_mbox_send()
2716 static void octeon_irq_ciu3_mbox_set_enable(struct irq_data *data, int cpu, bool en) in octeon_irq_ciu3_mbox_set_enable() argument
2722 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; in octeon_irq_ciu3_mbox_set_enable()
2724 intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox); in octeon_irq_ciu3_mbox_set_enable()
2725 ciu3_info = per_cpu(octeon_ciu3_info, cpu); in octeon_irq_ciu3_mbox_set_enable()
2726 isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn); in octeon_irq_ciu3_mbox_set_enable()
2727 isc_ctl_addr = ciu3_info->ciu3_addr + CIU3_ISC_CTL(intsn); in octeon_irq_ciu3_mbox_set_enable()
2735 unsigned int idt = per_cpu(octeon_irq_ciu3_idt_ip3, cpu); in octeon_irq_ciu3_mbox_set_enable()
2747 int cpu; in octeon_irq_ciu3_mbox_enable() local
2748 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; in octeon_irq_ciu3_mbox_enable()
2752 for_each_online_cpu(cpu) in octeon_irq_ciu3_mbox_enable()
2753 octeon_irq_ciu3_mbox_set_enable(data, cpu, true); in octeon_irq_ciu3_mbox_enable()
2758 int cpu; in octeon_irq_ciu3_mbox_disable() local
2759 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; in octeon_irq_ciu3_mbox_disable()
2763 for_each_online_cpu(cpu) in octeon_irq_ciu3_mbox_disable()
2764 octeon_irq_ciu3_mbox_set_enable(data, cpu, false); in octeon_irq_ciu3_mbox_disable()
2773 unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0; in octeon_irq_ciu3_mbox_ack()
2781 isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn); in octeon_irq_ciu3_mbox_ack()
2798 u64 b = ciu3_info->ciu3_addr; in octeon_irq_ciu3_alloc_resources()
2817 /* ip2 interrupts for this CPU */ in octeon_irq_ciu3_alloc_resources()
2822 /* ip3 interrupts for this CPU */ in octeon_irq_ciu3_alloc_resources()
2827 /* ip4 interrupts for this CPU */ in octeon_irq_ciu3_alloc_resources()
2863 .name = "CIU3-M",
2888 return -ENOMEM; in octeon_irq_init_ciu3()
2894 ciu3_info->ciu3_addr = base_addr = (u64)phys_to_virt(res.start); in octeon_irq_init_ciu3()
2895 ciu3_info->node = node; in octeon_irq_init_ciu3()
2909 /* Only do per CPU things if it is the CIU of the boot node. */ in octeon_irq_init_ciu3()
2925 ciu3_info->domain[i] = domain; in octeon_irq_init_ciu3()
2930 /* Only do per CPU things if it is the CIU of the boot node. */ in octeon_irq_init_ciu3()
2945 {.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu},
2946 {.compatible = "cavium,octeon-3860-gpio", .data = octeon_irq_init_gpio},
2947 {.compatible = "cavium,octeon-6880-ciu2", .data = octeon_irq_init_ciu2},
2948 {.compatible = "cavium,octeon-7890-ciu3", .data = octeon_irq_init_ciu3},
2949 {.compatible = "cavium,octeon-7130-cib", .data = octeon_irq_init_cib},
2956 /* Set the default affinity to the boot cpu. */ in arch_init_irq()
2981 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); in plat_irq_dispatch()
3001 return ciu3_info->domain[block]; in octeon_irq_get_block_domain()