sifive\-blocks (full) in projects: linux

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Searched +full:sifive +full:- +full:blocks (Results 1 – 16 of 16) sorted by relevance

/linux/Documentation/devicetree/bindings/sifive/
H A D	sifive-blocks-ip-versioning.txt	1 DT compatible string versioning for SiFive open-source IP blocks 4 strings for open-source SiFive IP blocks. HDL for these IP blocks 7 https://github.com/sifive/sifive-blocks 9 IP block-specific DT compatible strings are contained within the HDL, 10 in the form "sifive,<ip-block-name><integer version number>". 12 An example is "sifive,uart0" from: 14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43 16 Until these IP blocks (or IP integration) support version 17 auto-discovery, the maintainers of these IP blocks intend to increment 19 interface to these IP blocks changes, or when the functionality of the [all …]
/linux/Documentation/devicetree/bindings/pwm/
H A D	pwm-sifive.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2020 SiFive, Inc. 4 --- 5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: SiFive PWM controller 11 - Paul Walmsley <paul.walmsley@sifive.com> 14 Unlike most other PWM controllers, the SiFive PWM controller currently 19 numbers can be found here - 21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm [all …]`
/linux/Documentation/devicetree/bindings/spi/
H A D	spi-sifive.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SiFive SPI controller 10 - Pragnesh Patel <pragnesh.patel@sifive.com> 11 - Paul Walmsley <paul.walmsley@sifive.com> 12 - Palmer Dabbelt <palmer@sifive.com> 15 - $ref: spi-controller.yaml# 20 - enum: [all …]`
/linux/Documentation/devicetree/bindings/serial/
H A D	sifive-serial.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SiFive asynchronous serial interface (UART) 10 - Pragnesh Patel <pragnesh.patel@sifive.com> 11 - Paul Walmsley <paul.walmsley@sifive.com> 12 - Palmer Dabbelt <palmer@sifive.com> 15 - $ref: serial.yaml# 20 - enum: [all …]`
/linux/arch/riscv/crypto/
H A D	aes-riscv64-zvkned.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */ 3 // This file is dual-licensed, meaning that you can use it under your 15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com> 16 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com> 41 // The generated code of this file depends on the following RISC-V extensions: 42 // - RV64I 43 // - RISC-V Vector ('V') with VLEN >= 128 44 // - RISC-V Vector AES block cipher extension ('Zvkned') 51 #include "aes-macros.S" 88 // t0 is the remaining length in 32-bit words. It's a multiple of 4. [all …]
H A D	aes-riscv64-zvkned-zvkb.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */ 3 // This file is dual-licensed, meaning that you can use it under your 14 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com> 39 // The generated code of this file depends on the following RISC-V extensions: 40 // - RV64I 41 // - RISC-V Vector ('V') with VLEN >= 128 42 // - RISC-V Vector AES block cipher extension ('Zvkned') 43 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb') 50 #include "aes-macros.S" 63 // LEN32 = number of blocks, rounded up, in 32-bit words. [all …]
H A D	aes-macros.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause / 3 // This file is dual-licensed, meaning that you can use it under your 15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com> 16 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com> 41 // This file contains macros that are shared by the other aes-.S files. The 42 // generated code of these macros depends on the following RISC-V extensions: 43 // - RV64I 44 // - RISC-V Vector ('V') with VLEN >= 128 45 // - RISC-V Vector AES block cipher extension ('Zvkned') 49 // - If AES-128, loads round keys into v1-v11 and jumps to \label128. [all …]
H A D	chacha-riscv64-zvkb.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */ 3 // This file is dual-licensed, meaning that you can use it under your 14 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com> 39 // The generated code of this file depends on the following RISC-V extensions: 40 // - RV64I 41 // - RISC-V Vector ('V') with VLEN >= 128 42 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb') 87 vror.vi \d0, \d0, 32 - 16 88 vror.vi \d1, \d1, 32 - 16 89 vror.vi \d2, \d2, 32 - 16 [all …]
H A D	sm3-riscv64-zvksh-zvkb.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */ 3 // This file is dual-licensed, meaning that you can use it under your 15 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com> 40 // The generated code of this file depends on the following RISC-V extensions: 41 // - RV64I 42 // - RISC-V Vector ('V') with VLEN >= 128 43 // - RISC-V Vector SM3 Secure Hash extension ('Zvksh') 44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb') 86 // Load the state and endian-swap each 32-bit word. 92 addi NUM_BLOCKS, NUM_BLOCKS, -1 [all …]
H A D	aes-riscv64-zvkned-zvbb-zvkg.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */ 3 // This file is dual-licensed, meaning that you can use it under your 14 // Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com> 39 // The generated code of this file depends on the following RISC-V extensions: 40 // - RV64I 41 // - RISC-V Vector ('V') with VLEN >= 128 && VLEN < 2048 42 // - RISC-V Vector AES block cipher extension ('Zvkned') 43 // - RISC-V Vector Bit-manipulation extension ('Zvbb') 44 // - RISC-V Vector GCM/GMAC extension ('Zvkg') 51 #include "aes-macros.S" [all …]
H A D	aes-riscv64-glue.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * AES using the RISC-V vector crypto extensions. Includes the bare block 4 * cipher and the ECB, CBC, CBC-CTS, CTR, and XTS modes. 9 * Copyright (C) 2023 SiFive, Inc. 10 * Author: Jerry Shih <jerry.shih@sifive.com> 69 * - zvkned's key expansion instructions don't support AES-192. in riscv64_aes_setkey() 70 * So, non-zvkned fallback code would be needed anyway. in riscv64_aes_setkey() 72 * - Users of AES in Linux usually don't change keys frequently. in riscv64_aes_setkey() 73 * So, key expansion isn't performance-critical. in riscv64_aes_setkey() 75 * - For single-block AES exposed as a "cipher" algorithm, it's in riscv64_aes_setkey() [all …]
H A D	sha512-riscv64-zvknhb-zvkb.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */ 3 // This file is dual-licensed, meaning that you can use it under your 15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com> 40 // The generated code of this file depends on the following RISC-V extensions: 41 // - RV64I 42 // - RISC-V Vector ('V') with VLEN >= 128 43 // - RISC-V Vector SHA-2 Secure Hash extension ('Zvknhb') 44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb') 70 // Do 4 rounds of SHA-512. w0 contains the current 4 message schedule words. 73 // computes 4 more message schedule words. w1-w3 contain the next 3 groups of 4 [all …]
H A D	sha256-riscv64-zvknha_or_zvknhb-zvkb.S	1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */ 3 // This file is dual-licensed, meaning that you can use it under your 15 // Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com> 40 // The generated code of this file depends on the following RISC-V extensions: 41 // - RV64I 42 // - RISC-V Vector ('V') with VLEN >= 128 43 // - RISC-V Vector SHA-2 Secure Hash extension ('Zvknha' or 'Zvknhb') 44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb') 85 // Do 4 rounds of SHA-256. w0 contains the current 4 message schedule words. 88 // computes 4 more message schedule words. w1-w3 contain the next 3 groups of 4 [all …]
/linux/drivers/tty/serial/
H A D	sifive.c	`1 // SPDX-License-Identifier: GPL-2.0+ 3 * SiFive UART driver 5 * Copyright (C) 2018-2019 SiFive 8 * - drivers/tty/serial/pxa.c 9 * - drivers/tty/serial/amba-pl011.c 10 * - drivers/tty/serial/uartlite.c 11 * - drivers/tty/serial/omap-serial.c 12 * - drivers/pwm/pwm-sifive.c 15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of 16 * SiFive FE310-G000 v2p3 [all …]`
/linux/drivers/clk/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0 59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs 66 This driver supports NCO (Numerically Controlled Oscillator) blocks 67 found on Apple SoCs such as t8103 (M1). The blocks are typically 88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. 98 multi-function device has one fixed-rate oscillator, clocked 129 be pre-programmed to support other configurations and features not yet 178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. 196 For example, the CDCE925 contains two PLLs with spread-spectrum 206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" [all …]
/linux/drivers/gpio/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0-only 47 this symbol, but new drivers should use the generic gpio-regmap 57 non-sleeping contexts. They can make bitbanged serial protocols 126 Enables support for the idio-16 library functions. The idio-16 library 128 ACCES IDIO-16 family such as the 104-IDIO-16 and the PCI-IDIO-16. 130 If built as a module its name will be gpio-idio-16. 136 tristate "GPIO driver for 74xx-ICs with MMIO access" 140 Say yes here to support GPIO functionality for 74xx-compatible ICs 155 If driver is built as a module it will be called gpio-altera. 316 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)" [all …]