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/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-microgea-stm32mp1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
9 compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "shared-dma-pool";
24 no-map;
28 compatible = "shared-dma-pool";
30 no-map;
[all …]
H A Dstm32mp157a-icore-stm32mp1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
9 compatible = "engicam,icore-stm32mp1", "st,stm32mp157";
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "shared-dma-pool";
24 no-map;
28 compatible = "shared-dma-pool";
30 no-map;
[all …]
H A Dstm32mp15xx-osd32.dtsi1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 #include "stm32mp15-pinctrl.dtsi"
9 #include <dt-bindings/mfd/st,stpmic1.h>
12 reserved-memory {
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "shared-dma-pool";
20 no-map;
24 compatible = "shared-dma-pool";
[all …]
H A Dstm32mp157c-odyssey-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
17 model = "Seeed Studio Odyssey-STM32MP157C SOM";
18 compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
25 reserved-memory {
[all …]
H A Dstm32mp15xx-dhcor-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
8 #include "stm32mp15-pinctrl.dtsi"
9 #include "stm32mp15xxac-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/mfd/st,stpmic1.h>
23 reserved-memory {
24 #address-cells = <1>;
25 #size-cells = <1>;
29 compatible = "shared-dma-pool";
[all …]
H A Dstm32mp157c-emstamp-argon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include "stm32mp15-pinctrl.dtsi"
10 #include "stm32mp15xxac-pinctrl.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/mfd/st,stpmic1.h>
23 stdout-path = "serial0:115200n8";
31 reserved-memory {
32 #address-cells = <1>;
33 #size-cells = <1>;
37 compatible = "shared-dma-pool";
[all …]
H A Dstm32mp157c-phycore-stm32mp15-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
4 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/leds/leds-pca9532.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
[all …]
H A Dstm32mp15x-mecio1-io.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include "stm32mp15-pinctrl.dtsi"
9 #include "stm32mp15xxaa-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
15 stdout-path = "serial0:1500000n8";
34 reserved-memory {
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "shared-dma-pool";
[all …]
/linux/include/net/
H A Dxsk_buff_pool.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <linux/dma-mapping.h>
28 dma_addr_t dma; member
30 struct xsk_buff_pool *pool; member
56 /* Protects generic receive in shared and non-shared umem mode. */
66 /* For performance reasons, each buff pool has its own array of dma_pages
90 * sockets share a single cq when the same netdev and queue id is shared.
97 * The low 12-bits of the addr will be 0 since this is the page address, so we
106 int xp_assign_dev(struct xsk_buff_pool *pool, struct net_device *dev,
108 int xp_assign_dev_shared(struct xsk_buff_pool *pool, struct xdp_sock *umem_xs,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam572x-idk-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include "am57xx-idk-common.dtsi"
9 #include "dra74-ipu-dsp-common.dtsi"
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
22 ipu2_memory_region: ipu2-memory@95800000 {
[all …]
H A Ddra72-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
15 reserved-memory {
16 #address-cells = <2>;
17 #size-cells = <2>;
20 ipu2_memory_region: ipu2-memory@95800000 {
21 compatible = "shared-dma-pool";
27 dsp1_memory_region: dsp1-memory@99000000 {
[all …]
H A Ddra72-evm-revc.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 #include <dt-bindings/net/ti-dp83867.h>
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
30 compatible = "shared-dma-pool";
[all …]
H A Dam571x-idk.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "dra7-mmc-iodelay.dtsi"
11 #include "dra72x-mmc-iodelay.dtsi"
12 #include "am57xx-idk-common.dtsi"
13 #include "dra7-ipu-dsp-common.dtsi"
17 compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
7 #include "mpfs-sev-kit-fabric.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-SoC SEV Kit";
13 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
28 reserved-memory {
29 #address-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos-mfc-reserved-memory.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 reserved-memory {
10 #address-cells = <1>;
11 #size-cells = <1>;
14 mfc_left: region-mfc-left {
15 compatible = "shared-dma-pool";
16 no-map;
21 mfc_right: region-mfc-right {
22 compatible = "shared-dma-pool";
23 no-map;
[all …]
/linux/drivers/usb/core/
H A Dbuffer.c1 // SPDX-License-Identifier: GPL-2.0
3 * DMA memory management for framework level HCD code (hc_driver)
17 #include <linux/dma-mapping.h>
25 * DMA-Coherent Buffers
28 /* FIXME tune these based on pool statistics ... */
44 pool_max[0] = 0; /* Don't use this pool */ in usb_init_pool_max()
52 * hcd_buffer_create - initialize buffer pools
57 * Call this as part of initializing a host controller that uses the dma
58 * memory allocators. It initializes some pools of dma-coherent memory that
59 * will be shared by all drivers using that controller.
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-m4f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hari Nagalla <hnagalla@ti.com>
11 - Mathieu Poirier <mathieu.poirier@linaro.org>
20 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
25 - ti,am64-m4fss
27 power-domains:
30 "#address-cells":
[all …]
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
/linux/drivers/tee/
H A Dtee_shm_pool.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/dma-buf.h>
12 static int pool_op_gen_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, in pool_op_gen_alloc() argument
16 struct gen_pool *genpool = pool->private_data; in pool_op_gen_alloc()
17 size_t a = max_t(size_t, align, BIT(genpool->min_alloc_order)); in pool_op_gen_alloc()
23 return -ENOMEM; in pool_op_gen_alloc()
26 shm->kaddr = (void *)va; in pool_op_gen_alloc()
27 shm->paddr = gen_pool_virt_to_phys(genpool, va); in pool_op_gen_alloc()
28 shm->size = s; in pool_op_gen_alloc()
30 * This is from a static shared memory pool so no need to register in pool_op_gen_alloc()
[all …]
H A Dtee_shm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2017, 2019-2021 Linaro Limited
7 #include <linux/dma-buf.h>
8 #include <linux/dma-mapping.h>
44 if (shm->pages) { in release_registered_pages()
45 if (shm->flags & TEE_SHM_USER_MAPPED) in release_registered_pages()
46 unpin_user_pages(shm->pages, shm->num_pages); in release_registered_pages()
48 shm_put_kernel_pages(shm->pages, shm->num_pages); in release_registered_pages()
50 kfree(shm->pages); in release_registered_pages()
58 if (shm->flags & TEE_SHM_DMA_MEM) { in tee_shm_release()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dtqma8xxs.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 #include <dt-bindings/net/ti-dp83867.h>
10 /delete-node/ &encoder_rpc;
22 clk_xtal25: clk-xtal25 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <25000000>;
28 reg_tqma8xxs_3v3: regulator-3v3 {
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
[all …]
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h1 /* SPDX-License-Identifier: GPL-2.0 */
41 /* RX DMA Top Registers */
45 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) argument
302 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) argument
304 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) argument
306 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) argument
308 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) argument
310 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) argument
311 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) argument
315 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) argument
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dmarvell,mmp-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP DMA controller
10 - Duje Mihanović <duje.mihanovic@skole.hr>
13 Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio.
18 - marvell,pdma-1.0
19 - marvell,adma-1.0
20 - marvell,pxa910-squ
[all …]
/linux/kernel/dma/
H A Dcoherent.c1 // SPDX-License-Identifier: GPL-2.0
3 * Coherent per-device memory handling.
10 #include <linux/dma-direct.h>
11 #include <linux/dma-map-ops.h>
25 if (dev && dev->dma_mem) in dev_get_coherent_memory()
26 return dev->dma_mem; in dev_get_coherent_memory()
33 if (mem->use_dev_dma_pfn_offset) in dma_get_device_base()
34 return phys_to_dma(dev, PFN_PHYS(mem->pfn_base)); in dma_get_device_base()
35 return mem->device_base; in dma_get_device_base()
46 return ERR_PTR(-EINVAL); in dma_init_coherent_memory()
[all …]

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