1 /* SPDX-License-Identifier: GPL-2.0 */
41 /* RX DMA Top Registers */
45 #define MVPP2_POOL_BUF_SIZE_REG(pool)		(0x180 + 4 * (pool))  argument
302 #define MVPP2_BM_POOL_BASE_REG(pool)		(0x6000 + ((pool) * 4))  argument
304 #define MVPP2_BM_POOL_SIZE_REG(pool)		(0x6040 + ((pool) * 4))  argument
306 #define MVPP2_BM_POOL_READ_PTR_REG(pool)	(0x6080 + ((pool) * 4))  argument
308 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool)	(0x60c0 + ((pool) * 4))  argument
310 #define MVPP2_BM_BPPI_READ_PTR_REG(pool)	(0x6100 + ((pool) * 4))  argument
311 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool)	(0x6140 + ((pool) * 4))  argument
315 #define MVPP2_BM_POOL_CTRL_REG(pool)		(0x6200 + ((pool) * 4))  argument
331 #define MVPP2_BM_INTR_CAUSE_REG(pool)		(0x6240 + ((pool) * 4))  argument
337 #define MVPP2_BM_INTR_MASK_REG(pool)		(0x6280 + ((pool) * 4))  argument
338 #define MVPP2_BM_PHY_ALLOC_REG(pool)		(0x6400 + ((pool) * 4))  argument
345 #define MVPP2_BM_PHY_RLS_REG(pool)		(0x6480 + ((pool) * 4))  argument
355 /* Packet Processor per-port counters */
420 /* Per-port registers */
490 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
491  * relative to port->base.
527 /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
531 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
601 	(((index) < (q)->last_desc) ? ((index) + 1) : 0)
719 /* Maximum number of T-CONTs of PON port */
759 #define MVPP2_TX_DESC_ALIGN		(MVPP2_DESC_ALIGNED_SIZE - 1)
776 		((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
849 	((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE)
851 #define MVPP2_MAX_RX_BUF_SIZE	(PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM)
860 /* There are 7 supported high-level flows */
938 #define MVPP2_BM_POOL_SIZE_MAX		(16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
949 /* BM short pool packet size
1032 /* Shared Packet Processor resources */
1034 	/* Shared registers' base addresses */
1075 	/* Are we using page_pool with per-cpu pools? */
1114 	/* Spinlocks for CM3 shared memory configuration */
1117 	/* Spinlock for shared PRS parser memory and shadow table */
1137 /* Per-CPU port control */
1174 	/* TCAM key and mask for C2-based steering. These fields should be
1208 	/* Per-port registers' base address */
1222 	/* Per-CPU port control */
1241 	/* Per-port work and its lock to gather hardware statistics */
1285  * layout of the transmit and reception DMA descriptors, and their
1400 	dma_addr_t dma;  member
1406 /* Per-CPU Tx queue control */
1410 	/* Number of Tx DMA descriptors in the descriptor ring */
1413 	/* Number of currently used Tx DMA descriptor in the
1421 	/* Number of Tx DMA descriptors reserved for each CPU */
1427 	/* Index of last TX DMA descriptor that was inserted */
1430 	/* Index of the TX DMA descriptor to be cleaned up */
1433 	/* DMA buffer for TSO headers */
1445 	/* Number of Tx DMA descriptors in the descriptor ring */
1448 	/* Number of currently used Tx DMA descriptor in the descriptor ring */
1451 	/* Per-CPU control of physical Tx queues */
1456 	/* Virtual address of thex Tx DMA descriptors array */
1459 	/* DMA address of the Tx DMA descriptors array */
1462 	/* Index of the last Tx DMA descriptor */
1465 	/* Index of the next Tx DMA descriptor to process */
1470 	/* RX queue number, in the range 0-31 for physical RXQs */
1479 	/* Virtual address of the RX DMA descriptors array */
1482 	/* DMA address of the RX DMA descriptors array */
1485 	/* Index of the last RX DMA descriptor */
1488 	/* Index of the next RX DMA descriptor to process */
1503 	/* Pool number in the range 0-7 */
1506 	/* Buffer Pointers Pool External (BPPE) size */
1510 	/* Number of buffers for this pool */
1512 	/* Pool buffer size */
1520 	/* BPPE DMA base address */
1523 	/* Ports using BM pool */
1528 	((addr) >= (txq_pcpu)->tso_headers_dma && \
1529 	 (addr) < (txq_pcpu)->tso_headers_dma + \
1530 	 (txq_pcpu)->size * TSO_HEADER_SIZE)
1569 	return -1;  in mvpp22_tai_ptp_clock_index()
1575 	return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;  in mvpp22_rx_hwtstamping()