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/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_enet.h2 * Copyright 2008-2012 Freescale Semiconductor Inc.
37 @Description Ethernet MAC-PHY Interface
48 E_ENET_IF_SGMII = 0x00080000, /**< SGMII interface */
72 @Description Enum for inter-module interrupts registration
168 /**< dTSEC Time-Stamp Receive Error */
172 /**< mEMAC Time-stamp FIFO ECC error interrupt;
177 /**< SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
178 and phy or backplane;
179 Note: 1000BaseX auto-negotiation relates only to interface between MAC
180 and phy/backplane, SGMII phy can still synchronize with far-end phy at
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fq
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H A Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
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H A Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
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H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-widt
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2018-2019 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
20 emi1-slot1 = &ls1046mdio_s1;
21 emi1-slot2 = &ls1046mdio_s2;
22 emi1-slot4 = &ls1046mdio_s4;
27 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
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H A Dfsl-lx2162a-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2023 Josua Mayer <josua@solid-run.com>
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
10 #include "fsl-lx2162a-sr-som.dtsi"
14 compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
35 stdout-path = "serial0:115200n8";
39 compatible = "gpio-leds";
41 led_sfp_at: led-sfp-at {
43 default-state = "off";
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H A Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
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H A Dfsl-ls1028a-qds-9999.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-24801 card in slot 1.
11 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 slot1_sgmii0: ethernet-phy@1c {
23 slot1_sgmii1: ethernet-phy@1d {
27 slot1_sgmii2: ethernet-phy@1e {
31 slot1_sgmii3: ethernet-phy@1f {
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H A Dfsl-ls1028a-qds-9999.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-24801 card in slot 1.
11 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 slot1_sgmii0: ethernet-phy@1c {
23 slot1_sgmii1: ethernet-phy@1d {
27 slot1_sgmii2: ethernet-phy@1e {
31 slot1_sgmii3: ethernet-phy@1f {
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H A Dfsl-ls1028a-qds-899b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-24801 card in slot 1.
11 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 slot1_sgmii0: ethernet-phy@1c {
23 slot1_sgmii1: ethernet-phy@1d {
27 slot1_sgmii2: ethernet-phy@1e {
31 slot1_sgmii3: ethernet-phy@1f {
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H A Dfsl-ls1028a-qds-899b.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-24801 card in slot 1.
11 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 slot1_sgmii0: ethernet-phy@1c {
23 slot1_sgmii1: ethernet-phy@1d {
27 slot1_sgmii2: ethernet-phy@1e {
31 slot1_sgmii3: ethernet-phy@1f {
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsocfpga-dwmac.txt9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
26 phy-mode: The phy mode the ethernet operates in
27 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
29 This device node has additional phandle dependency, the sgmii converter:
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H A Dqcom-emac.txt3 This network controller consists of two devices: a MAC and an SGMII
4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
6 phandle points to the external PHY node.
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle to the external PHY node
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
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H A Dmediatek-net.txt10 - compatible: Should be
11 "mediatek,mt2701-eth": for MT2701 SoC
12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 "mediatek,mt7622-eth": for MT7622 SoC
14 "mediatek,mt7629-eth": for MT7629 SoC
15 "ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC
16 - reg: Address and length of the register set for the device
17 - interrupts: Should contain the three frame engines interrupts in numeric
19 - clocks: the clock used by the core
20 - clock-names: the names of the clock listed in the clocks property. These are
[all …]
H A Dxilinx_axienet.txt2 --------------------------------------------------------
5 provides connectivity to an external ethernet PHY supporting different
6 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
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/freebsd/sys/contrib/ncsw/inc/
H A Denet_ext.h1 /* Copyright (c) 2008-2012 Freescale Semiconductor, Inc
45 #define ENET_NUM_OCTETS_PER_ADDRESS 6 /**< Number of octets (8-bit bytes) in an ethernet addres…
65 @Description Ethernet MAC-PHY Interface
76 e_ENET_IF_SGMII = E_ENET_IF_SGMII, /**< SGMII interface */
82 #define ENET_IF_SGMII_BASEX 0x80000000 /**< SGMII/QSGII interface with 1000BaseX
83 auto-negotiation between MAC and phy
85 Note: 1000BaseX auto-negotiation relates
86 only to interface between MAC and phy/backplane,
87 SGMII phy can still synchronize with far-end phy
95 e_ENET_HALF_DUPLEX, /**< Half-Duplex mode */
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,sa8775p-dwmac-sgmii-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SerDes/SGMII ethernet PHY controller
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
13 The SerDes PHY sits between the MAC and the external PHY and provides
18 const: qcom,sa8775p-dwmac-sgmii-phy
22 - description: serdes
27 clock-names:
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm958625-meraki-alamo.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm958625-meraki-mx6x-common.dtsi"
12 compatible = "gpio-keys-polled";
14 poll-interval = <20>;
16 button-reset {
24 compatible = "gpio-leds";
26 led-0 {
27 /* green:wan1-left */
29 function-enumerator = <0>;
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/freebsd/sys/contrib/device-tree/src/mips/cavium-octeon/
H A Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/mips/mscc/
H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
42 pinctrl-names = "default";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Dcn9131-cf-solidwan.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
29 #include "armada-cp115.dtsi"
41 compatible = "solidrun,cn9131-solidwan",
42 "solidrun,cn9130-sr-som", "marvell,cn9130";
67 compatible = "gpio-leds";
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/freebsd/sys/dts/powerpc/
H A Dp3041ds.dts4 * Copyright 2010-2011 Freescale Semiconductor Inc.
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
67 bman-portals@ff4000000 {
68 bman-portal@0 {
69 cpu-handle = <&cpu0>;
71 bman-portal@4000 {
72 cpu-handle = <&cpu1>;
74 bman-portal@8000 {
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