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/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
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H A Dmediatek,mt7988-xfi-tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7988 XFI T-PHY
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
15 MediaTek's 10G-capabale MT7988 SoC.
20 const: mediatek,mt7988-xfi-tphy
27 - description: XFI PHY clock
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H A Dqcom,msm8996-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
18 const: qcom,msm8996-qmp-pcie-phy
22 - description: serdes
24 "#address-cells":
27 "#size-cells":
35 clock-names:
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* SERDES Register */
16 /* SERDES defines */
17 #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
18 #define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
19 #define SERDES_RST BIT(2) /* Serdes Reset */
20 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
40 /* Cross-timestamping defines */
H A Ddwmac-intel.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
15 #include <linux/clk.h>
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
186 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
198 * struct xpsgtr_phy - representation of a lane
219 * struct xpsgtr_dev - representation of a ZynMP GT device
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
173 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
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H A Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
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H A Dphy-qcom-qmp-usbc.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
26 #include "phy-qcom-qmp-common.h"
28 #include "phy-qcom-qmp.h"
29 #include "phy-qcom-qmp-pcs-misc-v3.h"
33 /* set of registers with offsets different per-PHY */
288 u16 serdes; member
298 /* struct qmp_phy_cfg - per-PHY initialization config */
302 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
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H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
28 #include "phy-qcom-qmp-dp-com-v3.h"
70 /* set of registers with offsets different per-PHY */
482 u16 serdes; member
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H A Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
24 #include "phy-qcom-qmp-common.h"
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
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H A Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
25 #include "phy-qcom-qmp-pcs-misc-v3.h"
26 #include "phy-qcom-qmp-pcs-misc-v4.h"
27 #include "phy-qcom-qmp-pcs-usb-v4.h"
28 #include "phy-qcom-qmp-pcs-usb-v5.h"
29 #include "phy-qcom-qmp-pcs-usb-v6.h"
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/linux/drivers/phy/ti/
H A Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
3 * Wrapper driver for SERDES used in J721E
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
35 /* SERDES offsets */
125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
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H A Dphy-am654-serdes.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe SERDES driver for AM654x SoC
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
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/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
18 #include <linux/clk.h>
104 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
106 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
107 bool no_pwrcycle:1; /* Omit initial power-cycle */
236 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
246 bool no_pwrcycle:1; /* Omit initial power-cycle */
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/linux/drivers/phy/samsung/
H A Dphy-exynos5250-sata.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SATA SerDes(PHY) driver
10 #include <linux/clk.h>
50 struct clk *phyclk;
66 return -EFAULT; in wait_for_reg_status()
73 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_on()
82 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_off()
94 ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_init()
97 dev_err(&sata_phy->phy->dev, "phy init failed\n"); in exynos_sata_phy_init()
99 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
17 #include <linux/clk.h>
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
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/linux/drivers/net/ethernet/renesas/
H A Drswitch.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
8 #include <linux/dma-mapping.h>
45 iowrite32(RRC_RR, priv->addr + RRC); in rswitch_reset()
46 iowrite32(RRC_RR_CLR, priv->addr + RRC); in rswitch_reset()
51 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); in rswitch_clock_enable()
56 iowrite32(RCDC_RCD, priv->addr + RCDC); in rswitch_clock_disable()
88 val = ioread32(priv->addr + CABPIRM); in rswitch_bpool_config()
92 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); in rswitch_bpool_config()
94 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); in rswitch_bpool_config()
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
8 * None of the four SerDes lanes are used by the module, instead they are
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
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/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j722s-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
[all …]
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
56 /* hw-ids */
152 * ->L0s not L1 */
171 #define PM_CTRL_CLK_SWH_L1 BIT(13) /* en pcie clk sw in L1 */
179 #define PM_CTRL_SERDES_PD_EX_L1 BIT(6) /* power down serdes rx */
200 * serdes, not sw to 25M */
207 #define MASTER_CTRL_WAKEN_25M BIT(5) /* WAKE WO. PCIE CLK */
293 #define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */
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