Lines Matching +full:serdes +full:- +full:clk

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Vinod Koul <vkoul@kernel.org>
18     const: qcom,msm8996-qmp-pcie-phy
22       - description: serdes
24   "#address-cells":
27   "#size-cells":
35   clock-names:
37       - const: aux
38       - const: cfg_ahb
39       - const: ref
44   reset-names:
46       - const: phy
47       - const: common
48       - const: cfg
50   vdda-phy-supply: true
52   vdda-pll-supply: true
54   vddp-ref-clk-supply: true
57   "^phy@[0-9a-f]+$":
63           - description: TX
64           - description: RX
65           - description: PCS
69           - description: PIPE clock
71       clock-names:
74           - enum:
75               - pipe0
76               - pipe1
77               - pipe2
81           - description: PHY reset
83       reset-names:
86           - enum:
87               - lane0
88               - lane1
89               - lane2
91       "#clock-cells":
94       clock-output-names:
97       "#phy-cells":
101       - reg
102       - clocks
103       - resets
104       - "#clock-cells"
105       - clock-output-names
106       - "#phy-cells"
111   - compatible
112   - reg
113   - "#address-cells"
114   - "#size-cells"
115   - ranges
116   - clocks
117   - clock-names
118   - resets
119   - reset-names
120   - vdda-phy-supply
121   - vdda-pll-supply
126   - |
127     #include <dt-bindings/clock/qcom,gcc-msm8996.h>
128     pcie_phy: phy-wrapper@34000 {
129         compatible = "qcom,msm8996-qmp-pcie-phy";
131         #address-cells = <1>;
132         #size-cells = <1>;
138         clock-names = "aux", "cfg_ahb", "ref";
143         reset-names = "phy", "common", "cfg";
145         vdda-phy-supply = <&vreg_l28a_0p925>;
146         vdda-pll-supply = <&vreg_l12a_1p8>;
156             #clock-cells = <0>;
157             clock-output-names = "pcie_0_pipe_clk_src";
159             #phy-cells = <0>;
170             #clock-cells = <0>;
171             clock-output-names = "pcie_1_pipe_clk_src";
173             #phy-cells = <0>;
184             #clock-cells = <0>;
185             clock-output-names = "pcie_2_pipe_clk_src";
187             #phy-cells = <0>;