Lines Matching +full:serdes +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
27 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
28 num-lanes = <1>;
29 #reset-cells = <1>;
30 #clock-cells = <1>;
32 assigned-clocks = <&k3_clks 279 1>;
33 assigned-clock-parents = <&k3_clks 279 5>;
35 serdes0: serdes@f000000 {
36 compatible = "ti,j721e-serdes-10g";
38 reg-names = "torrent_phy";
40 reset-names = "torrent_reset";
43 clock-names = "refclk", "phy_en_refclk";
44 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
47 assigned-clock-parents = <&k3_clks 279 1>,
50 #address-cells = <1>;
51 #size-cells = <0>;
52 #clock-cells = <1>;
59 compatible = "ti,am64-wiz-10g";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
65 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
66 num-lanes = <1>;
67 #reset-cells = <1>;
68 #clock-cells = <1>;
70 assigned-clocks = <&k3_clks 280 1>;
71 assigned-clock-parents = <&k3_clks 280 5>;
73 serdes1: serdes@f010000 {
74 compatible = "ti,j721e-serdes-10g";
76 reg-names = "torrent_phy";
78 reset-names = "torrent_reset";
81 clock-names = "refclk", "phy_en_refclk";
82 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
85 assigned-clock-parents = <&k3_clks 280 1>,
88 #address-cells = <1>;
89 #size-cells = <0>;
90 #clock-cells = <1>;
97 compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
102 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
106 interrupt-names = "link_state";
109 max-link-speed = <3>;
110 num-lanes = <1>;
111 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
113 clock-names = "fck", "pcie_refclk";
114 #address-cells = <3>;
115 #size-cells = <2>;
116 bus-range = <0x0 0xff>;
117 vendor-id = <0x104c>;
118 device-id = <0xb010>;
119 cdns,no-bar-match-nbits = <64>;
120 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
121 msi-map = <0x0 &gic_its 0x0 0x10000>;
126 compatible = "ti,j721e-usb";
128 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
130 clock-names = "ref", "lpm";
131 assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
132 assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
133 #address-cells = <2>;
134 #size-cells = <2>;
143 reg-names = "otg",
149 interrupt-names = "host",
152 maximum-speed = "super-speed";
158 compatible = "ti,am62-r5fss";
159 #address-cells = <1>;
160 #size-cells = <1>;
163 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
167 compatible = "ti,am62-r5f";
170 reg-names = "atcm", "btcm";
172 firmware-name = "j722s-main-r5f0_0-fw";
174 ti,sci-dev-id = <262>;
175 ti,sci-proc-ids = <0x04 0xff>;
176 ti,atcm-enable = <1>;
177 ti,btcm-enable = <1>;
183 compatible = "ti,am62a-c7xv-dsp";
185 reg-names = "l2sram";
187 firmware-name = "j722s-c71_0-fw";
189 ti,sci-dev-id = <208>;
190 ti,sci-proc-ids = <0x30 0xff>;
195 compatible = "ti,am62a-c7xv-dsp";
197 reg-names = "l2sram";
199 firmware-name = "j722s-c71_1-fw";
201 ti,sci-dev-id = <268>;
202 ti,sci-proc-ids = <0x31 0xff>;
210 firmware-name = "j722s-mcu-r5f0_0-fw";
216 firmware-name = "j722s-wkup-r5f0_0-fw";
220 serdes_ln_ctrl: mux-controller@4080 {
221 compatible = "reg-mux";
223 #mux-control-cells = <1>;
224 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
229 compatible = "ti,am62-audio-refclk";
232 assigned-clocks = <&k3_clks 157 18>;
233 assigned-clock-parents = <&k3_clks 157 33>;
234 #clock-cells = <0>;
239 pcie0_ctrl: pcie0-ctrl@4070 {
240 compatible = "ti,j784s4-pcie-ctrl", "syscon";
251 ti,interrupt-ranges = <7 71 21>;
255 pinctrl-single,gpio-range =
264 main_pmx0_range: gpio-range {
265 #pinctrl-single,gpio-range-cells = <3>;
270 gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
276 gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
278 gpio-reserved-ranges = <0 7>, <32 10>;