| /linux/rust/kernel/sync/ |
| H A D | aref.rs | 1 // SPDX-License-Identifier: GPL-2.0
7 //! from Rust; instead of making users have to use an additional Rust-reference count in the form of
29 /// Rust code, the recommendation is to use [`Arc`](crate::sync::Arc) to create reference-counted
37 /// Implementers must also ensure that all instances are reference-counted. (Otherwise they
58 /// An owned reference to an always-reference-counted object.
66 /// The pointer stored in `ptr` is non-null and valid for the lifetime of the [`ARef`] instance. In
73 // SAFETY: It is safe to send `ARe
[all...] |
| /linux/arch/arm64/boot/dts/apple/ |
| H A D | t600x-nvme.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4";
11 interrupt-parent = <&aic>;
16 interrupt-names = "send-empty", "send-not-empty",
17 "recv-empty", "recv-not-empty";
18 power-domains = <&DIE_NODE(ps_ans2)>;
19 #mbox-cells = <0>;
23 compatible = "apple,t6000-sart";
25 power-domains = <&DIE_NODE(ps_ans2)>;
29 compatible = "apple,t6000-nvme-ans2", "apple,nvme-ans2";
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | uncore-interconnect.json | 164 "BriefDescription": "BL Ingress Occupancy - DRS",
189 "BriefDescription": "BL Ingress Occupancy - NCB",
214 "BriefDescription": "BL Ingress Occupancy - NCS",
236 …ny requests behind it in the switch queue will lose ownership and have to re-acquire it later when…
256 …ddition to the source queue. Note the special filtering equation. We do OR-reduction on the requ…
266 …ddition to the source queue. Note the special filtering equation. We do OR-reduction on the requ…
276 …ddition to the source queue. Note the special filtering equation. We do OR-reduction on the requ…
286 …ddition to the source queue. Note the special filtering equation. We do OR-reduction on the requ…
341 …er of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not …
363 "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
[all …]
|
| H A D | uncore-cache.json | 15 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
24 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
34 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
44 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
54 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
64 …- this includes code, data, prefetches and hints coming from L2. This has numerous filters availa…
209 "BriefDescription": "LRU Queue; Non-0 Aged Victim",
214 "PublicDescription": "How often we picked a victim that had a non-zero age",
224 …T -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
234 …T -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-interconnect.json | 111 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
116 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
121 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
126 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
131 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
136 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
141 "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
146 "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
151 "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
156 "PublicDescription": "Counts Timeouts - Se
[all...] |
| H A D | uncore-cache.json | 27 "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
111 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
214 "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
227 "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
233 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
244 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
254 "PublicDescription": "Counts the number of times the LLC was accessed - thi
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | uncore-interconnect.json | 111 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
116 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
121 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
126 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
131 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
136 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
141 "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
146 "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
151 "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
156 "PublicDescription": "Counts Timeouts - Se
[all...] |
| H A D | uncore-cache.json | 27 "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
111 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
214 "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
227 "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
233 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
244 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
254 "PublicDescription": "Counts the number of times the LLC was accessed - thi
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | stall.json | 4 …send any micro-operations to the rename stage because of frontend resource stalls caused by fetch …
8 …send any micro-operations to the backend of the pipeline because of backend resource constraints. …
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-interconnect.json | 31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
144 … "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
154 "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | uncore-interconnect.json | 31 "BriefDescription": "FAF - request insert from TC.",
47 "BriefDescription": "FAF allocation -- sent to ADQ",
84 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
94 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
104 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
114 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
124 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
134 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
144 … "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
154 "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
[all …]
|
| /linux/Documentation/networking/caif/ |
| H A D | caif.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 :Copyright: |copy| ST-Ericsson AB 2010
40 The use of Start-of-frame-extension (STX) must also be set as
59 /sys/kernel/debug/caif_serial/<tty-name>/
61 * ser_state: Prints the bit-mask status where
63 - 0x02 means SENDING, this is a transient state.
64 - 0x10 means FLOW_OFF_SENT, i.e. the previous frame has not been sent
65 and is blocking further send operation. Flow OFF has been propagated
68 * tty_status: Prints the bit-mask tty status information
70 - 0x01 - tty->warned is on.
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | stall.json | 4 …send any micro-operations to the rename stage because of frontend resource stalls caused by fetch …
8 …send any micro-operations to the backend of the pipeline because of backend resource constraints. …
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | uncore-interconnect.json | 157 "BriefDescription": "FAF allocation -- sent to ADQ",
186 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
196 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
206 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
216 "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
226 "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
236 "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
246 "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
256 "BriefDescription": "Misc Events - Se
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | uncore-interconnect.json | 157 "BriefDescription": "FAF allocation -- sent to ADQ",
186 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
196 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
206 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
216 "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
226 "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
236 "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
246 "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
256 "BriefDescription": "Misc Events - Se
[all...] |
| /linux/arch/sh/include/asm/ |
| H A D | smc37c93x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * linux/include/asm-sh/smc37c93x.h
97 #define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
132 #define MCR_RTS 0x0200 /* Request to Send */
144 #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
145 #define LSR_TEMT 0x4000 /* Transmitter Empty */
150 #define MSR_DCTS 0x0100 /* Delta Clear to Send */
154 #define MSR_CTS 0x1000 /* Clear to Send */
|
| /linux/drivers/tty/serial/ |
| H A D | atmel_serial.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
27 #define ATMEL_US_STTTO BIT(11) /* Start Time-out */
28 #define ATMEL_US_SENDA BIT(12) /* Send Address */
31 #define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */
34 #define ATMEL_US_RTSEN BIT(18) /* Request To Send Enable */
35 #define ATMEL_US_RTSDIS BIT(19) /* Request To Send Disable */
81 #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */
99 #define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */
100 #define ATMEL_US_TXEMPTY BIT(9) /* Transmitter Empty */
102 #define ATMEL_US_TXBUFE BIT(11) /* Transmission Buffer Empty */
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | uncore-interconnect.json | 111 "BriefDescription": "FAF allocation -- sent to ADQ",
148 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
158 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
168 … "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
178 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
188 "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
198 … "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
208 … "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
218 "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch",
228 "BriefDescription": "Misc Events - Set 1 : Lost Forward",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | uncore-cache.json | 15 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
31 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
41 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
51 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
61 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer…
161 …-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' directio…
171 …-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' directio…
181 …-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' directio…
191 …-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' directio…
201 …-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' directio…
[all …]
|
| /linux/drivers/i2c/busses/ |
| H A D | i2c-iop3xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* ------------------------------------------------------------------------- */
3 /* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c */
4 /* ------------------------------------------------------------------------- */
5 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
9 /* ------------------------------------------------------------------------- */
25 #define IOP3XX_ICR_TXEMPTY_IE 0x0100 /* 1=Transmit Empty Interrupt Enable */
34 * the user needs to ensure that the GPIO Output Data Register -
41 #define IOP3XX_ICR_MABORT 0x0010 /* 1=Send a STOP with no data
43 #define IOP3XX_ICR_TBYTE 0x0008 /* 1=Send/Receive a byte. i2c clears */
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | uncore-cache.json | 23 "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
41 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
51 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
61 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
71 "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
81 "PublicDescription": "Counts the number of times the LLC was accessed - thi
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | uncore-cache.json | 1113 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an…
1249 "BriefDescription": "Distress signal asserted : DPT Stalled - IV",
1255 …"PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles ei…
1260 "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit",
1266 …"PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of c…
1321 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1332 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1343 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1354 …s -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
1365 …T -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio…
[all …]
|
| /linux/sound/drivers/ |
| H A D | serial-u16550.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Added support for the Midiator MS-124T and for the MS-124W in
17 * More documentation can be found in serial-u16550.txt.
39 #define SNDRV_SERIAL_MS124T 1 /* Midiator MS-124T */
40 #define SNDRV_SERIAL_MS124W_SA 2 /* Midiator MS-12
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | frontend.json | 19 …ruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to…
27 …uction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to…
44 …instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.",
52 …ion": "Counts the number of instructions retired that were tagged because empty issue slots were s…
60 …ion": "Counts the number of instructions retired that were tagged because empty issue slots were s…
76 …ruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to…
92 …s line or being redirected by a jump and the instruction cache registers bytes are not present. -",
100 "BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.",
|
| /linux/drivers/net/wireless/intel/iwlwifi/mld/ |
| H A D | rx.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2024-2025 Intel Corporation
11 * enum iwl_mld_internal_rxq_notif_type - RX queue sync notif types
13 * @IWL_MLD_RXQ_EMPTY: empty sync notification
22 * struct iwl_mld_internal_rxq_notif - @iwl_rxq_sync_cmd internal data.
29 * @payload: data to send to RX queues based on the type (may be empty)
39 * struct iwl_mld_rx_queues_sync - RX queues sync data
|