| /linux/drivers/net/ethernet/marvell/prestera/ |
| H A D | prestera_rxtx.c | 102 /* protect SDMA with concurrent access from multiple CPUs */
107 struct prestera_sdma sdma; member
110 static int prestera_sdma_buf_init(struct prestera_sdma *sdma, in prestera_sdma_buf_init() argument
116 desc = dma_pool_alloc(sdma->desc_pool, GFP_DMA | GFP_KERNEL, &dma); in prestera_sdma_buf_init()
128 static u32 prestera_sdma_map(struct prestera_sdma *sdma, dma_addr_t pa) in prestera_sdma_map() argument
130 return sdma->map_addr + pa; in prestera_sdma_map()
133 static void prestera_sdma_rx_desc_init(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_init() argument
142 desc->buff = cpu_to_le32(prestera_sdma_map(sdma, buf)); in prestera_sdma_rx_desc_init()
150 static void prestera_sdma_rx_desc_set_next(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_set_next() argument
154 desc->next = cpu_to_le32(prestera_sdma_map(sdma, next)); in prestera_sdma_rx_desc_set_next()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_sdma.c | 33 /* SDMA CSA reside in the 3rd page of CSA */
37 * GPU SDMA IP block helpers function.
45 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
46 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_instance_from_ring()
47 ring == &adev->sdma.instance[i].page) in amdgpu_sdma_get_instance_from_ring()
48 return &adev->sdma.instance[i]; in amdgpu_sdma_get_instance_from_ring()
58 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
59 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_index_from_ring()
60 ring == &adev->sdma.instance[i].page) { in amdgpu_sdma_get_index_from_ring()
77 /* don't enable OS preemption on SDMA under SRIOV */ in amdgpu_sdma_get_csa_mc_addr()
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| H A D | sdma_v7_1.c | 121 int xcc_id = adev->sdma.instance[instance].xcc_id; in sdma_v7_1_get_reg_offset()
122 int xcc_inst = dev_inst % adev->sdma.num_inst_per_xcc; in sdma_v7_1_get_reg_offset()
240 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v7_1_ring_insert_nop() local
244 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v7_1_ring_insert_nop()
447 * sdma_v7_1_gfx_resume_instance - start/restart a certain sdma engine
467 ring = &adev->sdma.instance[i].ring; in sdma_v7_1_gfx_resume_instance()
544 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v7_1_gfx_resume_instance()
552 /* Set up sdma hang watchdog */ in sdma_v7_1_gfx_resume_instance()
651 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj, in sdma_v7_1_inst_free_ucode_buffer()
652 &adev->sdma.instance[i].sdma_fw_gpu_addr, in sdma_v7_1_inst_free_ucode_buffer()
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| H A D | sdma_v4_0.c | 601 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_setup_ulv()
626 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_init_microcode()
632 for every SDMA instance */ in sdma_v4_0_init_microcode()
785 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v4_0_ring_insert_nop() local
789 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_0_ring_insert_nop()
918 * @enable: enable SDMA RB/IB
926 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_gfx_enable()
960 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_page_stop()
1009 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_ctx_switch_enable()
1021 * Enable SDMA utilization. Its only supported on in sdma_v4_0_ctx_switch_enable()
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| H A D | sdma_v6_0.c | 243 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v6_0_ring_insert_nop() local
247 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v6_0_ring_insert_nop()
399 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_stop()
435 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_ctxempty_int_enable()
465 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_enable()
473 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine
492 ring = &adev->sdma.instance[i].ring; in sdma_v6_0_gfx_resume_instance()
567 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v6_0_gfx_resume_instance()
575 /* Set up sdma hang watchdog */ in sdma_v6_0_gfx_resume_instance()
635 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_resume()
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| H A D | sdma_v7_0.c | 246 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v7_0_ring_insert_nop() local
250 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v7_0_ring_insert_nop()
402 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_stop()
457 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_enable()
465 * sdma_v7_0_gfx_resume_instance - start/restart a certain sdma engine
485 ring = &adev->sdma.instance[i].ring; in sdma_v7_0_gfx_resume_instance()
562 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v7_0_gfx_resume_instance()
570 /* Set up sdma hang watchdog */ in sdma_v7_0_gfx_resume_instance()
636 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_resume()
663 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v12_0_free_ucode_buffer()
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| H A D | sdma_v4_4.c | 24 #include "sdma/sdma_4_4_0_offset.h"
25 #include "sdma/sdma_4_4_0_sh_mask.h"
35 * to calculate register offset for all the sdma instances */
180 /* the SDMA_EDC_COUNTER register in each sdma instance in sdma_v4_4_get_ras_error_count()
187 dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n", in sdma_v4_4_get_ras_error_count()
222 * SDMA RAS supports single bit uncorrectable error detection. in sdma_v4_4_query_ras_error_count_by_instance()
228 * SDMA RAS does not support correctable errors. in sdma_v4_4_query_ras_error_count_by_instance()
241 /* write 0 to EDC_COUNTER reg to clear sdma edc counters */ in sdma_v4_4_reset_ras_error_count()
243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_reset_ras_error_count()
256 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_query_ras_error_count()
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap2.dtsi | 62 dmas = <&sdma 9 &sdma 10>;
100 sdma: dma-controller@0 { label
101 compatible = "ti,omap2420-sdma", "ti,omap-sdma";
136 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
137 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
147 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
163 dmas = <&sdma 13>;
172 dmas = <&sdma 49 &sdma 50>;
182 dmas = <&sdma 51 &sdma 52>;
192 dmas = <&sdma 53 &sdma 54>;
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| /linux/arch/powerpc/include/asm/ |
| H A D | mpc52xx.h | 76 /* SDMA */
78 u32 taskBar; /* SDMA + 0x00 */
79 u32 currentPointer; /* SDMA + 0x04 */
80 u32 endPointer; /* SDMA + 0x08 */
81 u32 variablePointer; /* SDMA + 0x0c */
83 u8 IntVect1; /* SDMA + 0x10 */
84 u8 IntVect2; /* SDMA + 0x11 */
85 u16 PtdCntrl; /* SDMA + 0x12 */
87 u32 IntPend; /* SDMA + 0x14 */
88 u32 IntMask; /* SDMA + 0x18 */
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx53.dtsi | 270 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
297 dmas = <&sdma 24 1 0>,
298 <&sdma 25 1 0>;
554 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
566 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
652 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
684 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
713 sdma: dma-controller@63fb0000 { label
714 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
721 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
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| H A D | imx51.dtsi | 221 dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
246 dmas = <&sdma 24 1 0>,
247 <&sdma 25 1 0>;
434 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
446 dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
510 sdma: dma-controller@83fb0000 { label
511 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
518 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
561 dmas = <&sdma 28 0 0>,
562 <&sdma 29 0 0>;
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| H A D | imx6sx-sdb-sai.dts | 22 &sdma {
24 /* SDMA event remap for SAI1 */
25 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | Kconfig | 11 bool "HFI1 SDMA Order debug"
16 sdma completions for unit testing
18 bool "Config SDMA Verbosity"
23 SDMA debug
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| H A D | ipoib.h | 48 * @txreq: sdma transmit request
50 * @sdma_status: status returned by sdma engine
71 * @sent_txreqs: count of txreqs posted to sdma
76 * @complete_txreqs: count of txreqs completed by sdma
98 * @sde: sdma engine
100 * @sent_txreqs: count of txreqs posted to sdma
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| H A D | sdma.h | 21 /* Hardware limit for SDMA packet size */
45 * count in submit_tx() in sdma.c
157 * DOC: sdma exported routines
159 * These sdma routines fit into three categories:
160 * - The SDMA API for building and submitting packets
164 * and tear down SDMA
171 * DOC: sdma PSM/verbs API
173 * The sdma API is designed to be used by both PSM
174 * and verbs to supply packets to the SDMA ring.
202 * SDMA interrupt handling.
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| /linux/drivers/gpu/drm/amd/include/ivsrcid/sdma3/ |
| H A D | irqsrcs_sdma3_5_0.h | 26 #define SDMA3_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
27 #define SDMA3_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
28 #define SDMA3_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
37 #define SDMA3_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
41 #define SDMA3_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
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| /linux/drivers/gpu/drm/amd/include/ivsrcid/sdma1/ |
| H A D | irqsrcs_sdma1_5_0.h | 25 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
26 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
27 #define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
36 #define SDMA1_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
40 #define SDMA1_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
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| H A D | irqsrcs_sdma1_4_0.h | 29 #define SDMA1_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA…
30 #define SDMA1_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA…
31 …A_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer …
40 #define SDMA1_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA…
44 #define SDMA1_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA…
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| /linux/drivers/gpu/drm/amd/include/ivsrcid/sdma2/ |
| H A D | irqsrcs_sdma2_5_0.h | 26 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
27 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
28 #define SDMA2_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
37 #define SDMA2_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
41 #define SDMA2_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
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| /linux/drivers/gpu/drm/amd/include/ivsrcid/sdma0/ |
| H A D | irqsrcs_sdma0_5_0.h | 25 #define SDMA0_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
26 #define SDMA0_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
27 #define SDMA0_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
36 #define SDMA0_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
40 #define SDMA0_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
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| H A D | irqsrcs_sdma0_4_0.h | 29 #define SDMA0_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA…
30 #define SDMA0_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA…
31 …A_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer …
40 #define SDMA0_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA…
44 #define SDMA0_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA…
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| /linux/include/soc/fsl/qe/ |
| H A D | immap_qe.h | 351 /* SDMA */
352 struct sdma { struct
355 __be32 sdtr1; /* SDMA system bus threshold register */
356 __be32 sdtr2; /* SDMA secondary bus threshold register */
357 __be32 sdhy1; /* SDMA system bus hysteresis register */
358 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
359 __be32 sdta1; /* SDMA system bus address register */
360 __be32 sdta2; /* SDMA secondary bus address register */
361 __be32 sdtm1; /* SDMA system bus MSNUM register */
362 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | fsl,imx8mp-aipstz.yaml | 95 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
102 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
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| /linux/drivers/gpu/drm/amd/include/ivsrcid/gfx/ |
| H A D | irqsrcs_gfx_11_0_0.h | 32 #define GFX_11_0_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 // 0x30 SDMA atomic*_rtn op…
36 #define GFX_11_0_0__SRCID__SDMA_PREEMPT 52 // 0x34 SDMA New Run List
37 #define GFX_11_0_0__SRCID__SDMA_IB_PREEMPT 53 // 0x35 sdma mid - command …
40 #define GFX_11_0_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 // 0x38 SDMA atomic CMPSWAP…
47 #define GFX_11_0_0__SRCID__SDMA_FROZEN 63 // 0x3F SDMA Frozen
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| H A D | irqsrcs_gfx_12_0_0.h | 30 #define GFX_12_0_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 // 0x30 SDMA atomic*_rtn ops complete
34 #define GFX_12_0_0__SRCID__SDMA_PREEMPT 52 // 0x34 SDMA New Run List
35 #define GFX_12_0_0__SRCID__SDMA_IB_PREEMPT 53 // 0x35 sdma mid - command buffer preempt interrupt
38 #define GFX_12_0_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 // 0x38 SDMA atomic CMPSWAP loop timeout
45 #define GFX_12_0_0__SRCID__SDMA_FROZEN 63 // 0x3F SDMA Frozen
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