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/linux/drivers/dma/
H A Dimx-sdma.c3 // drivers/dma/imx-sdma.c
47 /* SDMA registers */
105 * Error bit set in the CCB status field by the SDMA,
150 * 28 Lower WML Event(LWE) SDMA events reg to check for
154 * 29 Higher WML Event(HWE) SDMA events reg to check for
201 * struct sdma_script_start_addrs - SDMA script start pointers
204 * address space of the SDMA engine.
286 * @unused: padding. The SDMA engine expects an array of 128 byte
296 * struct sdma_state_registers - SDMA context for a channel
325 * struct sdma_context_data - sdma context specific to a channel
[all …]
/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_rxtx.c102 /* protect SDMA with concurrent access from multiple CPUs */
107 struct prestera_sdma sdma; member
110 static int prestera_sdma_buf_init(struct prestera_sdma *sdma, in prestera_sdma_buf_init() argument
116 desc = dma_pool_alloc(sdma->desc_pool, GFP_DMA | GFP_KERNEL, &dma); in prestera_sdma_buf_init()
128 static u32 prestera_sdma_map(struct prestera_sdma *sdma, dma_addr_t pa) in prestera_sdma_map() argument
130 return sdma->map_addr + pa; in prestera_sdma_map()
133 static void prestera_sdma_rx_desc_init(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_init() argument
142 desc->buff = cpu_to_le32(prestera_sdma_map(sdma, buf)); in prestera_sdma_rx_desc_init()
150 static void prestera_sdma_rx_desc_set_next(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_set_next() argument
154 desc->next = cpu_to_le32(prestera_sdma_map(sdma, next)); in prestera_sdma_rx_desc_set_next()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_sdma.c33 /* SDMA CSA reside in the 3rd page of CSA */
37 * GPU SDMA IP block helpers function.
45 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
46 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_instance_from_ring()
47 ring == &adev->sdma.instance[i].page) in amdgpu_sdma_get_instance_from_ring()
48 return &adev->sdma.instance[i]; in amdgpu_sdma_get_instance_from_ring()
58 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
59 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_index_from_ring()
60 ring == &adev->sdma.instance[i].page) { in amdgpu_sdma_get_index_from_ring()
77 /* don't enable OS preemption on SDMA under SRIOV */ in amdgpu_sdma_get_csa_mc_addr()
[all …]
H A Dsdma_v4_4_2.c35 #include "sdma/sdma_4_4_2_offset.h"
36 #include "sdma/sdma_4_4_2_sh_mask.h"
168 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
197 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
353 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v4_4_2_ring_insert_nop() local
357 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_4_2_ring_insert_nop()
434 << (ring->me % adev->sdma.num_inst_per_aid); in sdma_v4_4_2_ring_emit_hdp_flush()
494 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; in sdma_v4_4_2_inst_gfx_stop() local
500 sdma[i] = &adev->sdma.instance[i].ring; in sdma_v4_4_2_inst_gfx_stop()
512 if (sdma[i]->use_doorbell) { in sdma_v4_4_2_inst_gfx_stop()
[all …]
H A Dsdma_v6_0.c243 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v6_0_ring_insert_nop() local
247 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v6_0_ring_insert_nop()
399 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_stop()
435 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_ctxempty_int_enable()
465 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_enable()
473 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine
492 ring = &adev->sdma.instance[i].ring; in sdma_v6_0_gfx_resume_instance()
567 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v6_0_gfx_resume_instance()
575 /* Set up sdma hang watchdog */ in sdma_v6_0_gfx_resume_instance()
635 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_resume()
[all …]
H A Dsdma_v7_0.c247 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v7_0_ring_insert_nop() local
251 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v7_0_ring_insert_nop()
403 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_stop()
458 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_enable()
466 * sdma_v7_0_gfx_resume_instance - start/restart a certain sdma engine
486 ring = &adev->sdma.instance[i].ring; in sdma_v7_0_gfx_resume_instance()
563 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v7_0_gfx_resume_instance()
571 /* Set up sdma hang watchdog */ in sdma_v7_0_gfx_resume_instance()
637 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_resume()
664 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v12_0_free_ucode_buffer()
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H A Dsdma_v5_2.c231 /* SDMA seems to miss doorbells sometimes when powergating kicks in. in sdma_v5_2_ring_set_wptr()
257 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_2_ring_insert_nop() local
261 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_2_ring_insert_nop()
477 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
511 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_2_enable()
518 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
527 * sdma_v5_2_gfx_resume_instance - start/restart a certain sdma engine
548 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_gfx_resume_instance()
700 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
723 * sdma_v5_2_load_microcode - load the sDMA ME ucode
[all …]
H A Dsdma_v5_0.c294 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
409 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_insert_nop() local
413 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_insert_nop()
627 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
662 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_0_enable()
671 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
679 * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine
699 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_gfx_resume_instance()
853 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
876 * sdma_v5_0_load_microcode - load the sDMA ME ucode
[all …]
H A Dsdma_v4_4.c24 #include "sdma/sdma_4_4_0_offset.h"
25 #include "sdma/sdma_4_4_0_sh_mask.h"
35 * to calculate register offset for all the sdma instances */
180 /* the SDMA_EDC_COUNTER register in each sdma instance in sdma_v4_4_get_ras_error_count()
187 dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n", in sdma_v4_4_get_ras_error_count()
222 * SDMA RAS supports single bit uncorrectable error detection. in sdma_v4_4_query_ras_error_count_by_instance()
228 * SDMA RAS does not support correctable errors. in sdma_v4_4_query_ras_error_count_by_instance()
241 /* write 0 to EDC_COUNTER reg to clear sdma edc counters */ in sdma_v4_4_reset_ras_error_count()
243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_reset_ras_error_count()
256 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_query_ras_error_count()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap2.dtsi62 dmas = <&sdma 9 &sdma 10>;
100 sdma: dma-controller@0 { label
101 compatible = "ti,omap2420-sdma", "ti,omap-sdma";
136 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
137 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
147 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
163 dmas = <&sdma 13>;
172 dmas = <&sdma 49 &sdma 50>;
182 dmas = <&sdma 51 &sdma 52>;
192 dmas = <&sdma 53 &sdma 54>;
H A Domap3.dtsi181 dmas = <&sdma 9 &sdma 10>;
207 dmas = <&sdma 65 &sdma 66>;
289 sdma: dma-controller@0 { label
290 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
373 dmas = <&sdma 49 &sdma 50>;
383 dmas = <&sdma 51 &sdma 52>;
393 dmas = <&sdma 53 &sdma 54>;
448 dmas = <&sdma 35>,
449 <&sdma 36>,
450 <&sdma 37>,
[all …]
H A Domap2430.dtsi186 dmas = <&sdma 31>,
187 <&sdma 32>;
202 dmas = <&sdma 33>,
203 <&sdma 34>;
218 dmas = <&sdma 17>,
219 <&sdma 18>;
234 dmas = <&sdma 19>,
235 <&sdma 20>;
250 dmas = <&sdma 21>,
251 <&sdma 22>;
[all …]
/linux/drivers/infiniband/hw/hfi1/
H A Dvnic_sdma.c7 * This file contains HFI1 support for VNIC SDMA functionality
10 #include "sdma.h"
21 * @txreq: sdma transmit request
22 * @sdma: vnic sdma pointer
30 struct hfi1_vnic_sdma *sdma; member
42 struct hfi1_vnic_sdma *vnic_sdma = tx->sdma; in vnic_sdma_complete()
130 struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[q_idx]; in hfi1_vnic_send_dma()
147 tx->sdma = vnic_sdma; in hfi1_vnic_send_dma()
157 /* When -ECOMM, sdma callback will be called with ABORT status */ in hfi1_vnic_send_dma()
179 * hfi1_vnic_sdma_sleep - vnic sdma sleep function
[all …]
H A Dvnic.h10 #include "sdma.h"
33 * struct hfi1_vnic_sdma - VNIC per Tx ring SDMA information
35 * @sde - sdma engine
38 * @stx - sdma tx request
39 * @state - vnic Tx ring SDMA state
79 * @sdma: VNIC SDMA structure per TXQ
95 struct hfi1_vnic_sdma sdma[HFI1_VNIC_MAX_TXQ]; member
H A DKconfig11 bool "HFI1 SDMA Order debug"
16 sdma completions for unit testing
18 bool "Config SDMA Verbosity"
23 SDMA debug
/linux/arch/powerpc/include/asm/
H A Dmpc52xx.h76 /* SDMA */
78 u32 taskBar; /* SDMA + 0x00 */
79 u32 currentPointer; /* SDMA + 0x04 */
80 u32 endPointer; /* SDMA + 0x08 */
81 u32 variablePointer; /* SDMA + 0x0c */
83 u8 IntVect1; /* SDMA + 0x10 */
84 u8 IntVect2; /* SDMA + 0x11 */
85 u16 PtdCntrl; /* SDMA + 0x12 */
87 u32 IntPend; /* SDMA + 0x14 */
88 u32 IntMask; /* SDMA + 0x18 */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx31.dtsi135 dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
182 dmas = <&sdma 20 3 0>;
193 dmas = <&sdma 21 3 0>;
213 dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
248 dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
300 sdma: dma-controller@53fd4000 { label
301 compatible = "fsl,imx31-sdma";
307 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
348 dmas = <&sdma 30 17 0>;
H A Dimx53.dtsi270 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
297 dmas = <&sdma 24 1 0>,
298 <&sdma 25 1 0>;
554 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
566 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
652 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
684 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
713 sdma: dma-controller@63fb0000 { label
714 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
721 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
[all …]
H A Dimx51.dtsi221 dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
246 dmas = <&sdma 24 1 0>,
247 <&sdma 25 1 0>;
434 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
446 dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
510 sdma: dma-controller@83fb0000 { label
511 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
518 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
561 dmas = <&sdma 28 0 0>,
562 <&sdma 29 0 0>;
[all …]
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma3/
H A Dirqsrcs_sdma3_5_0.h26 #define SDMA3_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
27 #define SDMA3_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
28 #define SDMA3_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
37 #define SDMA3_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
41 #define SDMA3_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma1/
H A Dirqsrcs_sdma1_5_0.h25 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
26 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
27 #define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
36 #define SDMA1_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
40 #define SDMA1_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
H A Dirqsrcs_sdma1_4_0.h29 #define SDMA1_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA…
30 #define SDMA1_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA…
31 …A_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer …
40 #define SDMA1_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA…
44 #define SDMA1_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA…
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma2/
H A Dirqsrcs_sdma2_5_0.h26 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
27 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
28 #define SDMA2_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
37 #define SDMA2_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
41 #define SDMA2_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma0/
H A Dirqsrcs_sdma0_5_0.h25 #define SDMA0_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
26 #define SDMA0_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
27 #define SDMA0_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
36 #define SDMA0_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
40 #define SDMA0_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
H A Dirqsrcs_sdma0_4_0.h29 #define SDMA0_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA…
30 #define SDMA0_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA…
31 …A_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer …
40 #define SDMA0_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA…
44 #define SDMA0_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA…

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