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/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_rxtx.c102 /* protect SDMA with concurrent access from multiple CPUs */
107 struct prestera_sdma sdma; member
110 static int prestera_sdma_buf_init(struct prestera_sdma *sdma, in prestera_sdma_buf_init() argument
116 desc = dma_pool_alloc(sdma->desc_pool, GFP_DMA | GFP_KERNEL, &dma); in prestera_sdma_buf_init()
128 static u32 prestera_sdma_map(struct prestera_sdma *sdma, dma_addr_t pa) in prestera_sdma_map() argument
130 return sdma->map_addr + pa; in prestera_sdma_map()
133 static void prestera_sdma_rx_desc_init(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_init() argument
142 desc->buff = cpu_to_le32(prestera_sdma_map(sdma, buf)); in prestera_sdma_rx_desc_init()
150 static void prestera_sdma_rx_desc_set_next(struct prestera_sdma *sdma, in prestera_sdma_rx_desc_set_next() argument
154 desc->next = cpu_to_le32(prestera_sdma_map(sdma, next)); in prestera_sdma_rx_desc_set_next()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4_2.c35 #include "sdma/sdma_4_4_2_offset.h"
36 #include "sdma/sdma_4_4_2_sh_mask.h"
165 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
194 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
350 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v4_4_2_ring_insert_nop() local
354 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v4_4_2_ring_insert_nop()
431 << (ring->me % adev->sdma.num_inst_per_aid); in sdma_v4_4_2_ring_emit_hdp_flush()
491 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; in sdma_v4_4_2_inst_gfx_stop() local
497 sdma[i] = &adev->sdma.instance[i].ring; in sdma_v4_4_2_inst_gfx_stop()
509 if (sdma[i]->use_doorbell) { in sdma_v4_4_2_inst_gfx_stop()
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H A Dsdma_v7_1.c121 int xcc_id = adev->sdma.instance[instance].xcc_id; in sdma_v7_1_get_reg_offset()
122 int xcc_inst = dev_inst % adev->sdma.num_inst_per_xcc; in sdma_v7_1_get_reg_offset()
240 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v7_1_ring_insert_nop() local
244 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v7_1_ring_insert_nop()
447 * sdma_v7_1_gfx_resume_instance - start/restart a certain sdma engine
467 ring = &adev->sdma.instance[i].ring; in sdma_v7_1_gfx_resume_instance()
544 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v7_1_gfx_resume_instance()
552 /* Set up sdma hang watchdog */ in sdma_v7_1_gfx_resume_instance()
651 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj, in sdma_v7_1_inst_free_ucode_buffer()
652 &adev->sdma.instance[i].sdma_fw_gpu_addr, in sdma_v7_1_inst_free_ucode_buffer()
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H A Dsdma_v6_0.c244 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v6_0_ring_insert_nop() local
248 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v6_0_ring_insert_nop()
400 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_stop()
436 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_ctxempty_int_enable()
466 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_enable()
474 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine
493 ring = &adev->sdma.instance[i].ring; in sdma_v6_0_gfx_resume_instance()
568 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v6_0_gfx_resume_instance()
576 /* Set up sdma hang watchdog */ in sdma_v6_0_gfx_resume_instance()
636 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_resume()
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H A Dsdma_v7_0.c246 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v7_0_ring_insert_nop() local
250 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v7_0_ring_insert_nop()
402 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_stop()
457 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_enable()
465 * sdma_v7_0_gfx_resume_instance - start/restart a certain sdma engine
485 ring = &adev->sdma.instance[i].ring; in sdma_v7_0_gfx_resume_instance()
562 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v7_0_gfx_resume_instance()
570 /* Set up sdma hang watchdog */ in sdma_v7_0_gfx_resume_instance()
636 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_resume()
663 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v12_0_free_ucode_buffer()
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H A Dsdma_v5_2.c230 /* SDMA seems to miss doorbells sometimes when powergating kicks in. in sdma_v5_2_ring_set_wptr()
256 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_2_ring_insert_nop() local
260 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_2_ring_insert_nop()
476 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
510 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_2_enable()
517 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
526 * sdma_v5_2_gfx_resume_instance - start/restart a certain sdma engine
547 ring = &adev->sdma.instance[i].ring; in sdma_v5_2_gfx_resume_instance()
699 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
722 * sdma_v5_2_load_microcode - load the sDMA ME ucode
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H A Dsdma_v5_0.c293 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
408 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in sdma_v5_0_ring_insert_nop() local
412 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_insert_nop()
626 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
661 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_0_enable()
670 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
678 * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine
698 ring = &adev->sdma.instance[i].ring; in sdma_v5_0_gfx_resume_instance()
852 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
875 * sdma_v5_0_load_microcode - load the sDMA ME ucode
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H A Dsdma_v4_4.c24 #include "sdma/sdma_4_4_0_offset.h"
25 #include "sdma/sdma_4_4_0_sh_mask.h"
35 * to calculate register offset for all the sdma instances */
180 /* the SDMA_EDC_COUNTER register in each sdma instance in sdma_v4_4_get_ras_error_count()
187 dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n", in sdma_v4_4_get_ras_error_count()
222 * SDMA RAS supports single bit uncorrectable error detection. in sdma_v4_4_query_ras_error_count_by_instance()
228 * SDMA RAS does not support correctable errors. in sdma_v4_4_query_ras_error_count_by_instance()
241 /* write 0 to EDC_COUNTER reg to clear sdma edc counters */ in sdma_v4_4_reset_ras_error_count()
243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_reset_ras_error_count()
256 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_query_ras_error_count()
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/linux/arch/powerpc/include/asm/
H A Dmpc52xx.h76 /* SDMA */
78 u32 taskBar; /* SDMA + 0x00 */
79 u32 currentPointer; /* SDMA + 0x04 */
80 u32 endPointer; /* SDMA + 0x08 */
81 u32 variablePointer; /* SDMA + 0x0c */
83 u8 IntVect1; /* SDMA + 0x10 */
84 u8 IntVect2; /* SDMA + 0x11 */
85 u16 PtdCntrl; /* SDMA + 0x12 */
87 u32 IntPend; /* SDMA + 0x14 */
88 u32 IntMask; /* SDMA + 0x18 */
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/linux/drivers/infiniband/hw/hfi1/
H A DKconfig11 bool "HFI1 SDMA Order debug"
16 sdma completions for unit testing
18 bool "Config SDMA Verbosity"
23 SDMA debug
H A Dsdma.c19 #include "sdma.h"
31 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
35 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
39 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
43 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
46 /* max wait time for a SDMA engine to indicate it has halted */
48 /* all SDMA engine errors that cause a halt */
262 * sdma engine 'sde' to drop to 0.
297 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
346 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
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H A Dipoib.h48 * @txreq: sdma transmit request
50 * @sdma_status: status returned by sdma engine
71 * @sent_txreqs: count of txreqs posted to sdma
76 * @complete_txreqs: count of txreqs completed by sdma
98 * @sde: sdma engine
100 * @sent_txreqs: count of txreqs posted to sdma
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma3/
H A Dirqsrcs_sdma3_5_0.h26 #define SDMA3_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
27 #define SDMA3_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
28 #define SDMA3_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
37 #define SDMA3_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
41 #define SDMA3_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma1/
H A Dirqsrcs_sdma1_5_0.h25 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
26 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
27 #define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
36 #define SDMA1_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
40 #define SDMA1_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
H A Dirqsrcs_sdma1_4_0.h29 #define SDMA1_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA…
30 #define SDMA1_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA…
31 …A_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer …
40 #define SDMA1_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA…
44 #define SDMA1_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA…
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma2/
H A Dirqsrcs_sdma2_5_0.h26 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
27 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
28 #define SDMA2_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
37 #define SDMA2_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
41 #define SDMA2_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
/linux/drivers/gpu/drm/amd/include/ivsrcid/sdma0/
H A Dirqsrcs_sdma0_5_0.h25 #define SDMA0_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
26 #define SDMA0_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
27 #define SDMA0_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
36 #define SDMA0_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List
40 #define SDMA0_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen
H A Dirqsrcs_sdma0_4_0.h29 #define SDMA0_4_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 /* 0xD9 SDMA…
30 #define SDMA0_4_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 /* 0xDA SDMA…
31 …A_IB_PREEMPT 219 /* 0xDB sdma mid-command buffer …
40 #define SDMA0_4_0__SRCID__SDMA_PREEMPT 240 /* 0xF0 SDMA…
44 #define SDMA0_4_0__SRCID__SDMA_FROZEN 245 /* 0xF5 SDMA…
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53.dtsi270 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
297 dmas = <&sdma 24 1 0>,
298 <&sdma 25 1 0>;
554 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
566 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
652 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
684 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
713 sdma: dma-controller@63fb0000 { label
714 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
721 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
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H A Dimx51.dtsi221 dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
246 dmas = <&sdma 24 1 0>,
247 <&sdma 25 1 0>;
434 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
446 dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
510 sdma: dma-controller@83fb0000 { label
511 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
518 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
561 dmas = <&sdma 28 0 0>,
562 <&sdma 29 0 0>;
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H A Dimx6sx-sdb-sai.dts22 &sdma {
24 /* SDMA event remap for SAI1 */
25 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8mp-aipstz.yaml95 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
102 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
/linux/include/soc/fsl/qe/
H A Dimmap_qe.h351 /* SDMA */
352 struct sdma { struct
355 __be32 sdtr1; /* SDMA system bus threshold register */
356 __be32 sdtr2; /* SDMA secondary bus threshold register */
357 __be32 sdhy1; /* SDMA system bus hysteresis register */
358 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
359 __be32 sdta1; /* SDMA system bus address register */
360 __be32 sdta2; /* SDMA secondary bus address register */
361 __be32 sdtm1; /* SDMA system bus MSNUM register */
362 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
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/linux/drivers/gpu/drm/amd/include/ivsrcid/gfx/
H A Dirqsrcs_gfx_11_0_0.h32 #define GFX_11_0_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 // 0x30 SDMA atomic*_rtn op…
36 #define GFX_11_0_0__SRCID__SDMA_PREEMPT 52 // 0x34 SDMA New Run List
37 #define GFX_11_0_0__SRCID__SDMA_IB_PREEMPT 53 // 0x35 sdma mid - command …
40 #define GFX_11_0_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 // 0x38 SDMA atomic CMPSWAP…
47 #define GFX_11_0_0__SRCID__SDMA_FROZEN 63 // 0x3F SDMA Frozen
H A Dirqsrcs_gfx_12_0_0.h30 #define GFX_12_0_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 // 0x30 SDMA atomic*_rtn ops complete
34 #define GFX_12_0_0__SRCID__SDMA_PREEMPT 52 // 0x34 SDMA New Run List
35 #define GFX_12_0_0__SRCID__SDMA_IB_PREEMPT 53 // 0x35 sdma mid - command buffer preempt interrupt
38 #define GFX_12_0_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 // 0x38 SDMA atomic CMPSWAP loop timeout
45 #define GFX_12_0_0__SRCID__SDMA_FROZEN 63 // 0x3F SDMA Frozen

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