292 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_init_microcode()
438 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_insert_nop()  local
442 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_insert_nop()
599 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_stop()
658 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_ctx_switch_enable()
700 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_enable()
708  * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine
728 	ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_gfx_resume_instance()
882 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_gfx_resume()
905  * sdma_v5_0_load_microcode - load the sDMA ME ucode
922 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_load_microcode()
923 		if (!adev->sdma.instance[i].fw)  in sdma_v5_0_load_microcode()
926 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v5_0_load_microcode()
931 			(adev->sdma.instance[i].fw->data +  in sdma_v5_0_load_microcode()
942 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);  in sdma_v5_0_load_microcode()
977 	/* enable sdma ring preemption */  in sdma_v5_0_start()
1214  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1242  * Update PTEs by writing them manually using sDMA (NAVI10).
1263  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1272  * Update the page tables using sDMA (NAVI10).
1301 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);  in sdma_v5_0_ring_pad_ib()  local
1307 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v5_0_ring_pad_ib()
1344  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1351  * using sDMA (NAVI10).
1419 	/* SDMA trap event */  in sdma_v5_0_sw_init()
1422 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1426 	/* SDMA trap event */  in sdma_v5_0_sw_init()
1429 			      &adev->sdma.trap_irq);  in sdma_v5_0_sw_init()
1433 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_sw_init()
1434 		ring = &adev->sdma.instance[i].ring;  in sdma_v5_0_sw_init()
1438 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,  in sdma_v5_0_sw_init()
1446 		sprintf(ring->name, "sdma%d", i);  in sdma_v5_0_sw_init()
1447 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,  in sdma_v5_0_sw_init()
1455 	adev->sdma.supported_reset =  in sdma_v5_0_sw_init()
1456 		amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);  in sdma_v5_0_sw_init()
1461 		if (adev->sdma.instance[0].fw_version >= 35)  in sdma_v5_0_sw_init()
1462 			adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;  in sdma_v5_0_sw_init()
1468 	/* Allocate memory for SDMA IP Dump buffer */  in sdma_v5_0_sw_init()
1469 	ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);  in sdma_v5_0_sw_init()
1471 		adev->sdma.ip_dump = ptr;  in sdma_v5_0_sw_init()
1473 		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");  in sdma_v5_0_sw_init()
1487 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v5_0_sw_fini()
1488 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v5_0_sw_fini()
1493 	kfree(adev->sdma.ip_dump);  in sdma_v5_0_sw_fini()
1538 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_is_idle()
1581 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_reset_queue()
1582 		if (ring == &adev->sdma.instance[i].ring)  in sdma_v5_0_reset_queue()
1586 	if (i == adev->sdma.num_instances) {  in sdma_v5_0_reset_queue()
1587 		DRM_ERROR("sdma instance not found\n");  in sdma_v5_0_reset_queue()
1614 	/* check sdma copy engine all idle if frozen not received*/  in sdma_v5_0_reset_queue()
1618 			DRM_ERROR("cannot soft reset as sdma not idle\n");  in sdma_v5_0_reset_queue()
1733 	DRM_DEBUG("IH: SDMA trap\n");  in sdma_v5_0_process_trap_irq()
1754 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v5_0_process_trap_irq()
1770 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v5_0_process_trap_irq()
1800 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_clock_gating()
1802 			/* Enable sdma clock gating */  in sdma_v5_0_update_medium_grain_clock_gating()
1815 			/* Disable sdma clock gating */  in sdma_v5_0_update_medium_grain_clock_gating()
1837 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_update_medium_grain_light_sleep()
1839 			/* Enable sdma mem light sleep */  in sdma_v5_0_update_medium_grain_light_sleep()
1846 			/* Disable sdma mem light sleep */  in sdma_v5_0_update_medium_grain_light_sleep()
1912 	if (!adev->sdma.ip_dump)  in sdma_v5_0_print_ip_state()
1915 	drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);  in sdma_v5_0_print_ip_state()
1916 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_print_ip_state()
1922 				   adev->sdma.ip_dump[instance_offset + j]);  in sdma_v5_0_print_ip_state()
1933 	if (!adev->sdma.ip_dump)  in sdma_v5_0_dump_ip_state()
1937 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_dump_ip_state()
1940 			adev->sdma.ip_dump[instance_offset + j] =  in sdma_v5_0_dump_ip_state()
2007 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_ring_funcs()
2008 		adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;  in sdma_v5_0_set_ring_funcs()
2009 		adev->sdma.instance[i].ring.me = i;  in sdma_v5_0_set_ring_funcs()
2024 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +  in sdma_v5_0_set_irq_funcs()
2025 					adev->sdma.num_instances;  in sdma_v5_0_set_irq_funcs()
2026 	adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;  in sdma_v5_0_set_irq_funcs()
2027 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;  in sdma_v5_0_set_irq_funcs()
2031  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
2061  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
2096 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v5_0_set_buffer_funcs()
2113 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v5_0_set_vm_pte_funcs()
2115 				&adev->sdma.instance[i].ring.sched;  in sdma_v5_0_set_vm_pte_funcs()
2117 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;  in sdma_v5_0_set_vm_pte_funcs()