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/linux/drivers/reset/
H A Dreset-ti-sci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
19 * @dev_id: SoC-specific device identifier
20 * @reset_mask: reset mask to use for toggling reset
21 * @lock: synchronize reset_mask read-modify-writes
30 * struct ti_sci_reset_data - reset controller information structure
31 * @rcdev: reset controller entity
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/linux/Documentation/devicetree/bindings/arm/keystone/
H A Dti,sci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
27 specific functionality such as clocks, power domain, reset or additional
29 relationship between the TI-SCI parent node to the child node.
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H A Dti,k3-sci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common K3 TI-SCI
10 - Nishanth Menon <nm@ti.com>
14 that is responsible for managing various SoC-level resources like clocks,
16 through the TI-SCI protocol.
18 Each specific device management node like a clock controller node, a reset
19 controller node or an interrupt-controller node should define a common set
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j722s-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
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H A Dk3-j7200-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j721e-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-j721s2-mcu-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
9 sms: system-controller@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
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H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
24 #address-cells = <2>;
25 #size-cells = <2>;
27 #interrupt-cells = <3>;
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H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,j721s2-c71-dsp";
13 reg-names = "l2sram", "l1dram";
15 firmware-name = "j784s4-c71_3-fw";
16 ti,sci = <&sms>;
17 ti,sci-dev-id = <40>;
18 ti,sci-proc-ids = <0x33 0xff>;
23 compatible = "ti,j784s4-pcie-host";
30 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
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H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
31 - ti,am62a-c7xv-dsp
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H A Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
31 - reg: Should contain an entry for each value in 'reg-names'.
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/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7264.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh2a/clock-sh7264.c
34 * Default rate for the root input clock, reset this with clk_set_rate()
43 unsigned long rate = clk->parent->rate / pll1_div; in pll_recalc()
115 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP77]),
116 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP77]),
117 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP77]),
118 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP77]),
119 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP77]),
120 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP77]),
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H A Dclock-sh7269.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh2a/clock-sh7269.c
31 * Default rate for the root input clock, reset this with clk_set_rate()
40 return clk->parent->rate * PLL_RATE; in pll_recalc()
55 return clk->parent->rate / 8; in peripheral0_recalc()
70 return clk->parent->rate / 4; in peripheral1_recalc()
150 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP47]),
151 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP46]),
152 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP45]),
153 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP44]),
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/linux/drivers/scsi/isci/
H A Disci.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
118 * enum sci_status - This is the general return status enumeration for non-IO,
119 * non-task management related SCI interface methods.
171 * This member indicates that the SCI implementation is unable to complete
222 * requested information type is not supported by the SCI implementation.
240 * requested information type is not supported by the SCI implementation.
245 * This member indicates the calling function failed, because the SCI
251 * This member indicates the calling method failed, because the SCI
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/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7785.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7785.c
7 * Copyright (C) 2007 - 2010 Paul Mundt
20 * Default rate for the root input clock, reset this with clk_set_rate()
33 return clk->parent->rate * multiplier; in pll_recalc()
132 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
133 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
134 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
135 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
136 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
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H A Dclock-sh7786.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
18 * Default rate for the root input clock, reset this with clk_set_rate()
35 return clk->parent->rate * multiplier; in pll_recalc()
139 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
140 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
141 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
142 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
143 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
144 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),
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H A Dclock-shx3.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/clock-shx3.c
5 * SH-X3 support for the clock framework
7 * Copyright (C) 2006-2007 Renesas Technology Corp.
8 * Copyright (C) 2006-2007 Renesas Solutions Corp.
9 * Copyright (C) 2006-2010 Paul Mundt
19 * Default rate for the root input clock, reset this with clk_set_rate()
29 return clk->parent->rate * 72; in pll_recalc()
114 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
115 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
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H A Dclock-sh7757.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/clock-sh7757.c
7 * Copyright (C) 2009-2010 Renesas Solutions Corp.
17 * Default rate for the root input clock, reset this with clk_set_rate()
30 return clk->parent->rate * multiplier; in pll_recalc()
123 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]),
124 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP114]),
125 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP112]),
126 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP111]),
127 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP110]),
/linux/drivers/watchdog/
H A Dmachzwd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MachZ ZF-Logic Watchdog Timer driver for Linux
6 * any of this software. This material is provided "AS-IS" in
15 * wd#1 - 2 seconds;
16 * wd#2 - 7.2 ms;
17 * After the expiration of wd#1, it can generate a NMI, SCI, SMI, or
18 * a system RESET and it starts wd#2 that unconditionally will RESET
21 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
87 MODULE_DESCRIPTION("MachZ ZF-Logic Watchdog driver");
101 .identity = "ZF-Logic watchdog",
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/linux/drivers/infiniband/hw/hfi1/
H A Dpio.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015-2018 Intel Corporation.
18 * Set the CM reset bit and wait for it to clear. Use the provided
38 int flush = 0; /* re-read sendctrl to make sure it is flushed */ in pio_send_control()
41 spin_lock_irqsave(&dd->sendctrl_lock, flags); in pio_send_control()
50 for (i = 0; i < ARRAY_SIZE(dd->vld); i++) in pio_send_control()
51 if (!dd->vld[i].mtu) in pio_send_control()
86 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in pio_send_control()
93 #define SCS_POOL_0 -1
94 #define SCS_POOL_1 -2
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/linux/fs/nilfs2/
H A Dsegment.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2005-2008 Nippon Telegraph and Telephone Corporation.
18 #include <linux/backing-dev.h>
82 * wrapper functions of stage count (nilfs_sc_info->sc_stage.scnt). Users of
90 static inline void nilfs_sc_cstage_inc(struct nilfs_sc_info *sci) in nilfs_sc_cstage_inc() argument
92 sci->sc_stage.scnt++; in nilfs_sc_cstage_inc()
93 trace_nilfs2_collection_stage_transition(sci); in nilfs_sc_cstage_inc()
96 static inline void nilfs_sc_cstage_set(struct nilfs_sc_info *sci, int next_scnt) in nilfs_sc_cstage_set() argument
98 sci->sc_stage.scnt = next_scnt; in nilfs_sc_cstage_set()
99 trace_nilfs2_collection_stage_transition(sci); in nilfs_sc_cstage_set()
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/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Driver for Microsemi VSC85xx PHYs - MACsec support
11 #include <dt-bindings/net/mscc-phy-vsc8531.h>
37 /* non-MACsec access */ in vsc8584_macsec_phy_read()
185 /* Set the MACsec block out of s/w reset and enable clocks */ in vsc8584_macsec_block_init()
321 struct vsc8531_private *priv = phydev->priv; in __vsc8584_macsec_init()
358 proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2; in __vsc8584_macsec_init()
373 struct vsc8531_private *priv = phydev->priv; in vsc8584_macsec_flow()
374 enum macsec_bank bank = flow->bank; in vsc8584_macsec_flow()
375 u32 val, match = 0, mask = 0, action = 0, idx = flow->index; in vsc8584_macsec_flow()
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