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Searched +full:sci +full:- +full:intr (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/irqchip/
H A Dirq-ti-sci-intr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
23 * @sci: Pointer to TISCI handle
24 * @out_irqs: TISCI resource pointer representing INTR irqs.
26 * @ti_sci_id: TI-SCI device identifier
30 const struct ti_sci_handle *sci; member
38 .name = "INTR",
48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from
62 struct ti_sci_intr_irq_domain *intr = domain->host_data; in ti_sci_intr_irq_domain_translate() local
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Router (INTR) module provides a mechanism to mux M
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,am654-timer";
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
25 compatible = "ti,am654-timer";
28 clock-names = "fck";
29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
30 ti,timer-pwm;
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H A Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
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H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmcs.h1 /* SPDX-License-Identifier: GPL-2.0 */
105 u64 sci; member
161 void (*mcs_bbe_intr_handler)(struct mcs *mcs, u64 intr, enum mcs_direction dir);
162 void (*mcs_pab_intr_handler)(struct mcs *mcs, u64 intr, enum mcs_direction dir);
169 writeq(val, mcs->reg_base + offset); in mcs_reg_write()
174 return readq(mcs->reg_base + offset); in mcs_reg_read()
191 void mcs_rx_sc_cam_write(struct mcs *mcs, u64 sci, u64 secy, int sc_id);
212 /* CN10K-B APIs */
218 void cn10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir);
219 void cn10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir);
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H A Dmcs_cnf10kb.c1 // SPDX-License-Identifier: GPL-2.0
27 struct hwinfo *hw = mcs->hw; in cnf10kb_mcs_set_hw_capabilities()
29 hw->tcam_entries = 64; /* TCAM entries */ in cnf10kb_mcs_set_hw_capabilities()
30 hw->secy_entries = 64; /* SecY entries */ in cnf10kb_mcs_set_hw_capabilities()
31 hw->sc_entries = 64; /* SC CAM entries */ in cnf10kb_mcs_set_hw_capabilities()
32 hw->sa_entries = 128; /* SA entries */ in cnf10kb_mcs_set_hw_capabilities()
33 hw->lmac_cnt = 4; /* lmacs/ports per mcs block */ in cnf10kb_mcs_set_hw_capabilities()
34 hw->mcs_x2p_intf = 1; /* x2p clabration intf */ in cnf10kb_mcs_set_hw_capabilities()
35 hw->mcs_blks = 7; /* MCS blocks */ in cnf10kb_mcs_set_hw_capabilities()
36 hw->ip_vec = MCS_CNF10KB_INT_VEC_IP; /* IP vector */ in cnf10kb_mcs_set_hw_capabilities()
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H A Dmcs.c1 // SPDX-License-Identifier: GPL-2.0
32 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
35 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
38 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
41 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
44 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
47 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
50 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
53 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
56 stats->octet_encrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
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/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/keystone.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
32 #address-cells = <1>;
33 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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/linux/drivers/infiniband/hw/hfi1/
H A Dpio.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright(c) 2015-2017 Intel Corporation.
21 /* PIO release codes - in bits, as there could more than one that apply */
28 #define PRC_SC_DISABLE 0x20 /* clean-up after a context disable */
55 /* per-NUMA send context */
57 /* read-only after init */
91 u32 credit_intr_count; /* count of credit intr users */
132 * Since the mapping now allows for non-uniform send contexts per vl, the
148 * dd->pio_map
150 * | +--------------------+
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H A Dchip.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
32 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78 #define SEC_SC_HALTED 0x4 /* per-context only */
79 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
87 * 0 - User Fecn Handling
88 * 1 - Vnic
89 * 2 - AIP
90 * 3 - Verbs
101 #define emulator_rev(dd) ((dd)->irev >> 8)
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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