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/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
95 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
96 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
97 <&scg1 IMX7ULP_CLK_DDR_DIV>,
98 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
99 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
100 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
101 <&scg1 IMX7ULP_CLK_UPLL>,
102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
103 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
[all …]
H A Dimx7ulp-scg-clock.yaml24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
42 const: fsl,imx7ulp-scg1
81 compatible = "fsl,imx7ulp-scg1";
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-com.dts41 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
H A Dimx7ulp-evk.dts81 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
/linux/Documentation/devicetree/bindings/pwm/
H A Dimx-tpm-pwm.yaml56 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
/linux/Documentation/devicetree/bindings/watchdog/
H A Dfsl-imx7ulp-wdt.yaml59 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,tpm-timer.yaml62 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
/linux/include/dt-bindings/clock/
H A Dimx7ulp-clock.h11 /* SCG1 */
/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c68 /* SCG1 */ in imx7ulp_clk_scg1_init()
133 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);