| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
18 controller MUX memory resource if required.
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| H A D | fsl-sata.txt | 1 * Freescale 8xxx/3.0 Gb/s SATA nodes
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA port should have its own node.
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
10 "fsl,pq-sata"
11 - interrupts : <interrupt mapping for SATA IRQ>
12 - cell-index : controller index.
13 1 for controller @ 0x18000
14 2 for controller @ 0x19000
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| H A D | imx-sata.txt | 1 * Freescale i.MX AHCI SATA Controller
3 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
7 - compatible : should be one of the following:
8 - "fsl,imx53-ahci" for i.MX53 SATA controller
9 - "fsl,imx6q-ahci" for i.MX6Q SATA controller
10 - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
11 - interrupts : interrupt mapping for SATA IRQ
12 - reg : registers mapping
13 - clocks : list of clock specifiers, must contain an entry for each
14 required entry in clock-names
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| H A D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
15 controller implementation. It's hardware interface is supposed to
17 Advanced Host Controller Interface specification for details). The
18 document doesn't constitute a DT-node binding by itself but merely
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| H A D | exynos-sata.txt | 1 * Samsung AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
7 - compatible : compatible list, contains "samsung,exynos5-sata"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - samsung,sata-freq : <frequency in MHz>
11 - phys : Must contain exactly one entry as specified
12 in phy-bindings.txt
13 - phy-names : Must be "sata-phy"
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| H A D | sata-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial AT attachment (SATA) controllers
10 - Linus Walleij <linus.walleij@linaro.org>
14 AT attachment (SATA) storage devices. It doesn't constitute a device tree
18 The SATA controller-specific device tree bindings are responsible for
23 pattern: "^sata(@.*)?$"
25 Specifies the host controller node. SATA host controller nodes are named
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| H A D | faraday,ftide010.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Faraday Technology FTIDE010 PATA controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This controller is the first Faraday IDE interface block, used in the
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
19 SATA bridge in order to support SATA. This is why a phandle to that
20 controller is compulsory on that platform.
22 The timing properties are unique per-SoC, not per-board.
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| H A D | ahci-platform.txt | 1 * AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
6 It is possible, but not required, to represent each port as a sub-node.
11 - compatible : compatible string, one of:
12 - "brcm,iproc-ahci"
13 - "hisilicon,hisi-ahci"
14 - "cavium,octeon-7130-ahci"
15 - "ibm,476gtr-ahci"
16 - "marvell,armada-380-ahci"
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| H A D | imx-sata.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
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| H A D | ahci-platform.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
11 Each SATA controller should have its own node.
13 It is possible, but not required, to represent each port as a sub-node.
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
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| H A D | snps,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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| H A D | rockchip,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
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| H A D | brcm,sata-brcm.txt | 1 * Broadcom SATA3 AHCI Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
7 - compatible : should be one or more of
8 "brcm,bcm7216-ahci"
9 "brcm,bcm7425-ahci"
10 "brcm,bcm7445-ahci"
11 "brcm,bcm-nsp-ahci"
12 "brcm,sata3-ahci"
13 "brcm,bcm63138-ahci"
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| H A D | cortina,gemini-sata-bridge.txt | 1 * Cortina Systems Gemini SATA Bridge
3 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
5 them in different configurations to two SATA ports.
8 - compatible: should be
9 "cortina,gemini-sata-bridge"
10 - reg: registers and size for the block
11 - resets: phandles to the reset lines for both SATA bridges
12 - reset-names: must be "sata0", "sata1"
13 - clocks: phandles to the compulsory peripheral clocks
14 - clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
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| H A D | marvell.txt | 1 * Marvell Orion SATA
4 - compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
5 - reg : Address range of controller
6 - interrupts : Interrupt controller is using
7 - nr-ports : Number of SATA ports in use.
10 - phys : List of phandles to sata phys
11 - phy-names : Should be "0", "1", etc, one number per phandle
15 sata@80000 {
16 compatible = "marvell,orion-sata";
20 phy-names = "0", "1";
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| H A D | nvidia,tegra-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/sys/dev/isci/scil/ |
| H A D | scu_bios_definitions.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
64 * stand-alone where the library is excluded. By excluding
85 // For Intel Storage Controller Unit OEM Block
126 * stands for Intel Storage Controller Unit OEM Block.
162 * elements corresponds to the number of SCU controller units contained
185 * be set for the Intel SAS Storage Controller Unit (SCU).
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | samsung-phy.txt | 2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
17 - samsung,cam0-sysreg - phandle to the CAM0 system registers controller
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| H A D | phy-miphy365x.txt | 5 for SATA and PCIe.
7 Required properties (controller (parent) node):
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
17 nodes to describe the controller's topology. These nodes
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
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| H A D | qcom-ipq806x-sata-phy.txt | 1 Qualcomm IPQ806x SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,ipq806x-sata-phy"
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: must be exactly one entry
12 - clock-names: must be "cfg"
15 sata_phy: sata-phy@1b400000 {
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| H A D | nvidia,tegra124-xusb-padctl.txt | 1 Device tree binding for NVIDIA Tegra XUSB pad controller
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
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| H A D | qcom-apq8064-sata-phy.txt | 1 Qualcomm APQ8064 SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
5 Each SATA PHY controller should have its own node.
8 - compatible: compatible list, contains "qcom,apq8064-sata-phy".
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
12 clock-names.
13 - clock-names: must be "cfg" for phy config clock.
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| /freebsd/share/man/man4/ |
| H A D | aac.4 | 29 .Nd Adaptec AdvancedRAID Controller driver
34 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
53 and Ultra320, SATA and SAS RAID controllers.
60 device enables the SCSI pass-thru interface and allows devices connected
61 to the card such as CD-ROMs to be available via the CAM
68 device nodes provide access to the management interface of the controller.
81 Linux-compatible
84 Linux-based management applications to control the card.
90 .Bl -bullet -compact
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| H A D | ahci.4 | 1 .\" Copyright (c) 2009-2013 Alexander Motin <mav@FreeBSD.org>
30 .Nd Serial ATA Advanced Host Controller Interface driver
35 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
50 .Bl -ohang
52 controls Message Signaled Interrupts (MSI) usage by the specified controller.
54 .Bl -tag -width 4n -offset indent -compact
63 controls Command Completion Coalescing (CCC) usage by the specified controller.
64 Non-zero value enables CCC and defines maximum time (in ms), request can wait
65 for interrupt, if there are some more requests present on controller queue.
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| /freebsd/sys/contrib/device-tree/src/arm/gemini/ |
| H A D | gemini.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
20 compatible = "cortina,gemini-flash", "cfi-flash";
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