Lines Matching +full:sata +full:- +full:controller
1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
18 controller MUX memory resource if required.
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
24 * "sata-phy" for the SATA 6.0Gbps PHY
27 - dma-coherent : Present if dma operations are coherent
28 - status : Shall be "ok" if enabled or "disabled" if disabled.
33 compatible = "fixed-clock";
34 #clock-cells = <1>;
35 clock-frequency = <100000000>;
36 clock-output-names = "sataclk";
40 compatible = "apm,xgene-phy";
42 #phy-cells = <1>;
46 compatible = "apm,xgene-phy";
48 #phy-cells = <1>;
51 sata2: sata@1a400000 {
52 compatible = "apm,xgene-ahci";
59 dma-coherent;
62 phy-names = "sata-phy";
65 sata3: sata@1a800000 {
66 compatible = "apm,xgene-ahci-pcie";
73 dma-coherent;
76 phy-names = "sata-phy";