| /freebsd/sys/dev/e1000/ |
| H A D | e1000_regs.h | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 #define E1000_CTRL 0x00000 /* Device Control - RW */
39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
40 #define E1000_STATUS 0x00008 /* Device Status - RO */
41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
44 #define E1000_FLA 0x0001C /* Flash Access - RW */
45 #define E1000_MDIC 0x00020 /* MDI Control - RW */
[all …]
|
| /freebsd/sys/dev/mlx5/mlx5_accel/ |
| H A D | mlx5_ipsec_fs.c | 1 /*-
48 * TX tables are organized differently for Ethernet and for RoCE:
51 * Ethernet Tx | SA KSPI | match
52 * --------------------->|Flowtable|----->+ +
56 * DROP<--------+ |---->|Encrypt|------>|Flowtable|---->| TX NS |
61 * Tx |Flowtable|----->|Flowtable|---->+ |
62 * ---->|IP header| |ReqId+IP | |
63 * | | | header |--------------------------------+
67 * +-------------------------------------------------------
73 * Rx Tables and rules: +=========+
[all …]
|
| /freebsd/sys/dev/wtap/ |
| H A D | if_wtapioctl.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2010-2011 Monthadar Al Jaberi, TerraNet AB
7 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
36 * Ioctl-related defintions for the Wireless TAP
58 u_int32_t ast_rxorn; /* rx overrun interrupts */
59 u_int32_t ast_rxeol; /* rx eol interrupts */
60 u_int32_t ast_txurn; /* tx underrun interrupts */
67 u_int32_t ast_tx_encap; /* tx encapsulation failed */
68 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
[all …]
|
| /freebsd/sys/gnu/dev/bwn/phy_n/ |
| H A D | if_bwn_radio_2055.h | 22 Boston, MA 02110-1301, USA.
38 #define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
39 #define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
40 #define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
41 #define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
44 #define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
45 #define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
46 #define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
47 #define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
53 #define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
[all …]
|
| /freebsd/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_fman_port.h | 2 * Copyright 2008-2013 Freescale Semiconductor Inc.
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
[all …]
|
| /freebsd/sys/dev/eqos/ |
| H A D | if_eqos.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 * $Id: eqos.c 1059 2022-12-08 19:32:32Z sos $
33 * DesignWare Ethernet Quality-of-Service controller
84 #define TX_QUEUED(h, t) ((((h) - (t)) + TX_DESC_COUNT) % TX_DESC_COUNT)
93 #define EQOS_LOCK(sc) mtx_lock(&(sc)->lock)
94 #define EQOS_UNLOCK(sc) mtx_unlock(&(sc)->lock)
95 #define EQOS_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
97 #define RD4(sc, o) bus_read_4(sc->res[EQOS_RES_MEM], (o))
98 #define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v))
[all …]
|
| /freebsd/sys/dev/ath/ |
| H A D | if_athioctl.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
63 u_int32_t ast_rxorn; /* rx overrun interrupts */
64 u_int32_t ast_rxeol; /* rx eol interrupts */
65 u_int32_t ast_txurn; /* tx underrun interrupts */
72 u_int32_t ast_tx_encap; /* tx encapsulation failed */
73 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
74 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
[all …]
|
| /freebsd/sys/dev/igc/ |
| H A D | igc_regs.h | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
11 #define IGC_CTRL 0x00000 /* Device Control - RW */
12 #define IGC_STATUS 0x00008 /* Device Status - RO */
13 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
15 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
16 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
17 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
18 #define IGC_MDIC 0x00020 /* MDI Control - RW */
19 #define IGC_MDICNFG 0x00E04 /* MDI Config - RW */
[all …]
|
| /freebsd/sys/dev/rtwn/rtl8188e/ |
| H A D | r88e_calib.c | 1 /*-
2 * Copyright (c) 2016-2019 Andriy Voskoboinyk <avos@FreeBSD.org>
66 r88e_iq_calib_chain(struct rtwn_softc *sc, uint16_t tx[2], uint16_t rx[2]) in r88e_iq_calib_chain()
70 /* Set Rx IQ calibration mode table. */ in r88e_iq_calib_chain()
101 return (0); /* Tx failed. */ in r88e_iq_calib_chain()
103 /* Read Tx IQ calibration results. */ in r88e_iq_calib_chain()
104 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(0)), in r88e_iq_calib_chain()
106 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(0)), in r88e_iq_calib_chain()
108 if (tx[0] == 0x142 || tx[1] == 0x042) in r88e_iq_calib_chain()
109 return (0); /* Tx failed. */ in r88e_iq_calib_chain()
[all …]
|
| /freebsd/sys/dev/rtwn/rtl8192c/pci/ |
| H A D | r92ce_calib.c | 3 /*-
71 r92ce_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], in r92ce_iq_calib_chain()
72 uint16_t rx[2]) in r92ce_iq_calib_chain()
82 if (sc->ntxchains > 1) { in r92ce_iq_calib_chain()
111 return (0); /* Tx failed. */ in r92ce_iq_calib_chain()
112 /* Read Tx IQ calibration results. */ in r92ce_iq_calib_chain()
113 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)), in r92ce_iq_calib_chain()
115 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), in r92ce_iq_calib_chain()
117 if (tx[0] == 0x142 || tx[1] == 0x042) in r92ce_iq_calib_chain()
118 return (0); /* Tx failed. */ in r92ce_iq_calib_chain()
[all …]
|
| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
[all …]
|
| /freebsd/sys/dev/neta/ |
| H A D | if_mvneta.c | 111 /* Rx/Tx Queue Control */
159 /* Tx Subroutines */
166 /* Rx Subroutines */
191 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx)
192 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx)
270 "rx_good_oct", "Good Octets Rx"},
272 "rx_bad_oct", "Bad Octets Rx"},
276 "rx_good_frame", "Good Frames Rx"},
278 "rx_bad_frame", "Bad Frames Rx"},
280 "rx_bcast_frame", "Broadcast Frames Rx"},
[all …]
|
| /freebsd/sys/dev/vge/ |
| H A D | if_vgereg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
55 #define VGE_TXCTL 0x07 /* TX control register */
81 #define VGE_TXHOSTERR 0x22 /* TX host error status */
82 #define VGE_RXHOSTERR 0x23 /* RX host error status */
86 #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */
[all …]
|
| /freebsd/sys/dev/rtwn/rtl8192c/ |
| H A D | r92c_calib.c | 3 /*-
71 r92c_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], in r92c_iq_calib_chain()
72 uint16_t rx[2]) in r92c_iq_calib_chain()
82 if (sc->ntxchains > 1) { in r92c_iq_calib_chain()
111 return (0); /* Tx failed. */ in r92c_iq_calib_chain()
112 /* Read Tx IQ calibration results. */ in r92c_iq_calib_chain()
113 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)), in r92c_iq_calib_chain()
115 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)), in r92c_iq_calib_chain()
117 if (tx[0] == 0x142 || tx[1] == 0x042) in r92c_iq_calib_chain()
118 return (0); /* Tx failed. */ in r92c_iq_calib_chain()
[all …]
|
| /freebsd/sys/dev/cas/ |
| H A D | if_casreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
73 #define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */
75 #define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
88 #define CAS_INTR_TX_ALL 0x00000002 /* TX frames trans. to FIFO. */
89 #define CAS_INTR_TX_DONE 0x00000004 /* Any TX frame transferred. */
90 #define CAS_INTR_TX_TAG_ERR 0x00000008 /* TX FIFO tag corrupted. */
[all …]
|
| /freebsd/sys/arm/allwinner/ |
| H A D | if_awg.c | 1 /*-
71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | rockchip,i2s-tdm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
[all …]
|
| H A D | davinci-mcasp-audio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
[all …]
|
| /freebsd/sys/net80211/ |
| H A D | ieee80211_ioctl.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
42 uint32_t ns_rx_data; /* rx data frames */
43 uint32_t ns_rx_mgmt; /* rx management frames */
44 uint32_t ns_rx_ctrl; /* rx control frames */
45 uint32_t ns_rx_ucast; /* rx unicast frames */
46 uint32_t ns_rx_mcast; /* rx multi/broadcast frames */
47 uint64_t ns_rx_bytes; /* rx data count (bytes) */
48 uint64_t ns_rx_beacons; /* rx beacon frames */
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/renesas/ |
| H A D | r8a7794.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car E2 (R8A77940) SoC
9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7794-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
[all …]
|
| H A D | r8a7793.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
37 compatible = "fixed-clock";
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | micrel-ksz90x1.txt | 8 Note that these settings are applied after any phy-specific fixup from
17 skew values actually increase in 120ps steps, starting from -840ps. The
28 -----------------------------------------------------
29 0 -840ps 0000
30 200 -720ps 0001
31 400 -600ps 0010
32 600 -480ps 0011
33 800 -360ps 0100
34 1000 -240ps 0101
35 1200 -120ps 0110
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap2430.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,omap2-l4-wkup", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
21 compatible = "ti,omap2-prcm";
25 #address-cells = <1>;
26 #size-cells = <0>;
34 compatible = "ti,omap2-scm", "simple-bus";
36 #address-cells = <1>;
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | ena.4 | 1 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
67 processing by providing multiple Tx/Rx queue pairs (the maximum number
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
69 interrupt vector per Tx/Rx queue pair, and CPU cacheline optimized
[all …]
|
| /freebsd/sys/contrib/libsodium/src/libsodium/crypto_kx/ |
| H A D | crypto_kx.c | 34 crypto_kx_client_session_keys(unsigned char rx[crypto_kx_SESSIONKEYBYTES], in crypto_kx_client_session_keys()
35 unsigned char tx[crypto_kx_SESSIONKEYBYTES], in crypto_kx_client_session_keys()
45 if (rx == NULL) { in crypto_kx_client_session_keys()
46 rx = tx; in crypto_kx_client_session_keys()
48 if (tx == NULL) { in crypto_kx_client_session_keys()
49 tx = rx; in crypto_kx_client_session_keys()
51 if (rx == NULL) { in crypto_kx_client_session_keys()
55 return -1; in crypto_kx_client_session_keys()
66 rx[i] = keys[i]; in crypto_kx_client_session_keys()
67 tx[i] = keys[i + crypto_kx_SESSIONKEYBYTES]; in crypto_kx_client_session_keys()
[all …]
|