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/linux/Documentation/devicetree/bindings/serial/
H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
38 rx-tx-swap: true
[all …]
H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
34 dcd-gpios:
40 dsr-gpios:
46 dtr-gpios:
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/linux/tools/testing/selftests/bpf/
H A Dxdp_hw_metadata.c1 // SPDX-License-Identifier: GPL-2.0
6 * RX:
7 * - UDP 9091 packets are diverted into AF_XDP
8 * - Metadata verified:
9 * - rx_timestamp
10 * - rx_hash
12 * TX:
13 * - UDP 9091 packets trigger TX reply
14 * - TX HW timestamp is requested and reported back upon completion
15 * - TX checksum is requested
[all …]
/linux/drivers/tty/serial/
H A Dstm32-usart.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DRIVER_NAME "stm32-usart"
192 #define RX_BUF_L 4096 /* dma rx buffer length */
193 #define RX_BUF_P (RX_BUF_L / 2) /* dma rx buffer period */
194 #define TX_BUF_L RX_BUF_L /* dma tx buffer length */
202 struct dma_chan *rx_ch; /* dma rx channel */
203 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
204 unsigned char *rx_buf; /* dma rx buffer cpu address */
205 struct dma_chan *tx_ch; /* dma tx channel */
206 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
[all …]
/linux/drivers/video/fbdev/
H A Dpxa168fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* ------------< LCD register >------------ */
177 #define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */ argument
179 #define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */ argument
185 #define CFG_RXBITSTO0(rx) ((rx) << 5) argument
187 #define CFG_TXBITSTO0(tx) ((tx) << 4) argument
198 /* SPI Tx Data Register */
202 1. Smart Pannel 8-bit Bus Control Register.
236 #define CFG_GRA_SWAPRB(swap) ((swap) << 12) argument
238 #define CFG_GRA_SWAPUV(swap) ((swap) << 11) argument
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/linux/Documentation/devicetree/bindings/mtd/
H A Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
[all …]
/linux/include/uapi/linux/
H A Dserial_reg.h1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
44 #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
61 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
132 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
142 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
200 #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
222 #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
223 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
224 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
225 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
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/linux/Documentation/devicetree/bindings/net/
H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/linux/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/shared/msgq/inc/msgq/
H A Dmsgq_priv.h4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
7 …* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights rese…
8 * SPDX-License-Identifier: MIT
30 * msgqTxHeader -- TX queue data structure
36 * @flags: 1 = swap the RX pointers
42 * GSP. The status queue is a queue of messages/responses from GSP-RM to the
44 * queue is owned by the driver and the status queue is owned by GSP-RM. In
52 * This is enforced by the concept of "swapping" the RX pointers. This is
76 NvU32 msgSize; // entry size, bytes, must be power-of-2, 16 is minimum
79 NvU32 flags; // if set it means "i want to swap RX"
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dpm6150.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/iio/qcom,spmi-vadc.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/spmi/spmi.h>
10 #include <dt-bindings/thermal/thermal.h>
13 thermal-zones {
14 pm6150_thermal: pm6150-thermal {
15 polling-delay-passive = <100>;
17 thermal-sensors = <&pm6150_temp>;
[all …]
H A Dpm8150b.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/iio/qcom,spmi-vadc.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/spmi/spmi.h>
12 thermal-zones {
13 pm8150b-thermal {
14 polling-delay-passive = <100>;
16 thermal-sensors = <&pm8150b_temp>;
43 compatible = "qcom,pm8150b", "qcom,spmi-pmic";
[all …]
H A Dpm7250b.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/iio/qcom,spmi-vadc.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/spmi/spmi.h>
11 thermal-zones {
12 pm7250b-thermal {
13 polling-delay-passive = <100>;
15 thermal-sensors = <&pm7250b_temp>;
42 compatible = "qcom,pm7250b", "qcom,spmi-pmic";
44 #address-cells = <1>;
[all …]
/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
[all …]
/linux/drivers/net/ethernet/sun/
H A Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
45 /* The following registers are for per-qe channel information/status. */
48 #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
49 #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
50 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
51 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
54 #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
55 #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
56 #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
[all …]
/linux/drivers/net/ethernet/amazon/ena/
H A Dena_admin_defs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
13 /* customer metrics - in correlation with
136 /* Bypass Rx UDP ordering */
150 * 1 : ctrl_data - control buffer address valid
151 * 2 : ctrl_data_indirect - control buffer address
173 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
224 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
230 /* 3:0 : placement_policy - Describing where the SQ
232 * 0x1 - descriptors and headers are in OS memory,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
57 #define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
[all …]
/linux/drivers/net/ethernet/sfc/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
99 "Reducing number of rx queues from %u to %u.\n", in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Defx_channels.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !efx_siena_rss_cpus, in efx_wanted_parallelism()
100 "Reducing number of rx queues from %u to %u.\n", in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
110 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
[all …]
/linux/net/can/j1939/
H A Dtransport.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2010-2011 EIA Electronics,
6 // Copyright (c) 2017-2019 Pengutronix,
7 // Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2017-2019 Pengutronix,
13 #include "j1939-priv.h"
229 netdev_warn(priv->ndev, "Unknown abort code %i", abort); in j1939_xtp_abort_to_errno()
238 spin_lock_bh(&priv->active_session_list_lock); in j1939_session_list_lock()
243 spin_unlock_bh(&priv->active_session_list_lock); in j1939_session_list_unlock()
248 kref_get(&session->kref); in j1939_session_get()
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Dce.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
12 /* Byte swap data words */
25 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
36 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
38 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
43 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
44 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
108 /* #entries in source ring - Must be a power of 2 */
117 /* #entries in destination ring - Must be a power of 2 */
[all …]
/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
68 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
70 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
71 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
[all …]
/linux/drivers/net/ethernet/amd/
H A D7990.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * 7990.h -- LANCE ethernet IC generic routines.
11 * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
25 * reorder queued Tx packets based on priority. [Clearly there is a minimum
26 * limit too: too small and we drop rx packets and can't tx at full speed.]
32 * too long (and overflow the RAM on shared-memory cards like the HP LANCE.
41 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
42 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
71 * init block,the Tx and Rx rings and the buffers together in memory:
74 volatile unsigned short mode; /* Pre-set mode (reg. 15) */
[all …]
/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ argument
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */ argument
394 #define CFG_RXBITSTO0(rx) ((rx)<<5) argument
396 #define CFG_TXBITSTO0(tx) ((tx)<<4) argument
407 /* SPI Tx Data Register */
411 1. Smart Pannel 8-bit Bus Control Register.
[all …]
/linux/sound/soc/fsl/
H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
[all …]
/linux/drivers/net/ethernet/cadence/
H A Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
33 #define MACB_RBQP 0x0018 /* RX Q Base Address */
34 #define MACB_TBQP 0x001c /* TX Q Base Address */
86 #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
100 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
101 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
113 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
[all …]

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