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/linux/sound/soc/meson/
H A Daxg-card.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <sound/soc-dai.h>
11 #include "axg-tdm.h"
12 #include "meson-card.h"
16 u32 rx; member
21 unsigned int slots; member
30 * Those will be over-written by the CPU side of the link
44 struct meson_card *priv = snd_soc_card_get_drvdata(rtd->card); in axg_card_tdm_be_hw_params()
46 (struct axg_dai_link_tdm_data *)priv->link_data[rtd->id]; in axg_card_tdm_be_hw_params()
48 return meson_card_i2s_set_sysclk(substream, params, be->mclk_fs); in axg_card_tdm_be_hw_params()
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/linux/drivers/net/ethernet/google/gve/
H A Dgve_rx.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
19 dma_addr_t dma = (dma_addr_t)(be64_to_cpu(data_slot->addr) & in gve_rx_free_buffer()
22 page_ref_sub(page_info->page, page_info->pagecnt_bias - 1); in gve_rx_free_buffer()
23 gve_free_page(dev, page_info->page, dma, DMA_FROM_DEVICE); in gve_rx_free_buffer()
27 struct gve_rx_ring *rx, in gve_rx_unfill_pages() argument
30 u32 slots = rx->mask + 1; in gve_rx_unfill_pages() local
33 if (!rx->data.page_info) in gve_rx_unfill_pages()
36 if (rx->data.raw_addressing) { in gve_rx_unfill_pages()
37 for (i = 0; i < slots; i++) in gve_rx_unfill_pages()
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/linux/Documentation/devicetree/bindings/net/
H A Dlitex,liteeth.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Joel Stanley <joel@jms.id.au>
17 https://github.com/enjoy-digital/liteeth/.
20 - $ref: ethernet-controller.yaml#
28 - description: MAC registers
29 - description: MDIO registers
30 - description: Packet buffer
32 reg-names:
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H A Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
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/linux/Documentation/devicetree/bindings/sound/
H A Ddavinci-mcasp-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
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H A Dtdm-slot.txt6 dai-tdm-slot-num : Number of slots in use.
7 dai-tdm-slot-width : Width in bits for each slot.
8 dai-tdm-slot-tx-mask : Transmit direction slot mask, optional
9 dai-tdm-slot-rx-mask : Receive direction slot mask, optional
12 dai-tdm-slot-num = <2>;
13 dai-tdm-slot-width = <8>;
14 dai-tdm-slot-tx-mask = <0 1>;
15 dai-tdm-slot-rx-mask = <1 0>;
18 to specify an explicit mapping of the channels and the slots. If it's absent
20 tx and rx masks.
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/linux/sound/soc/fsl/
H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
13 // one FIFO which combines all valid receive slots. We cannot even select
14 // which slots we want to receive. The WM9712 with which this driver
16 // we receive in our (PCM-) data stream. The only chance we have is to
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
56 #define RX 0 macro
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H A Dfsl_esai.c1 // SPDX-License-Identifier: GPL-2.0
17 #include "imx-pcm.h"
25 * struct fsl_esai_soc_data - soc specific data
33 * struct fsl_esai - ESAI private data
45 * @fifo_depth: depth of tx/rx FIFO
47 * @slots: number of slots
49 * @rx_mask: slot mask for RX
50 * @channels: channel num for tx or rx
56 * @synchronous: if using tx/rx synchronous mode
73 u32 slots; member
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H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
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/linux/tools/testing/selftests/hid/tests/
H A Dtest_sony.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
43 for x in range(-32000, 32000, 4000):
51 # to inverse calibration, followed by calibration by hid-sony.
52 assert x - 1 <= value <= x + 1
54 for y in range(-32000, 32000, 4000):
61 assert y - 1 <= value <= y + 1
63 for z in range(-32000, 32000, 4000):
70 assert z - 1 <= value <= z + 1
76 for rx in range(-2000000, 2000000, 200000):
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - fsl,mpc885-scc-qmc
21 - fsl,mpc866-scc-qmc
22 - const: fsl,cpm1-scc-qmc
26 - description: SCC (Serial communication controller) register base
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H A Dfsl,qe-ucc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
26 - description: Dual port ram base
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H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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H A Dfsl,ucc-hdlc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-Level Data Link Control(HDLC)
12 - Frank Li <Frank.Li@nxp.com>
16 const: fsl,ucc-hdlc
24 cell-index:
27 rx-clock-name:
30 - pattern: "^brg([0-9]|1[0-6])$"
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/linux/sound/soc/
H A Dsoc-dai.c1 // SPDX-License-Identifier: GPL-2.0
3 // soc-dai.c
10 #include <sound/soc-dai.h>
11 #include <sound/soc-link.h>
23 case -EPROBE_DEFER: in _soc_dai_ret()
24 case -ENOTSUPP: in _soc_dai_ret()
27 dev_err(dai->dev, in _soc_dai_ret()
29 func, dai->name, ret); in _soc_dai_ret()
39 #define soc_dai_mark_push(dai, substream, tgt) ((dai)->mark_##tgt = substream)
40 #define soc_dai_mark_pop(dai, tgt) ((dai)->mark_##tgt = NULL)
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/linux/drivers/net/
H A Dxen-netfront.c4 * Copyright (c) 2002-2005, K A Fraser
81 #define NETFRONT_SKB_CB(skb) ((struct netfront_cb *)((skb)->cb))
88 /* Minimum number of Rx slots (includes slot for GSO metadata). */
91 /* Queue name is interface name with "-qNNN" appended */
94 /* IRQ name is queue name with "-tx" or "-rx" appended */
108 unsigned int id; /* Queue ID, 0-based */
109 char name[QUEUE_NAME_SIZE]; /* DEVNAME-qN */
122 char tx_irq_name[IRQ_NAME_SIZE]; /* DEVNAME-qN-tx */
123 char rx_irq_name[IRQ_NAME_SIZE]; /* DEVNAME-qN-rx */
130 * {tx,rx}_skbs store outstanding skbuffs. Free tx_skb entries
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/linux/sound/soc/intel/boards/
H A Dsof_maxim_common.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <sound/soc-acpi.h>
10 #include <sound/soc-dai.h>
11 #include <sound/soc-dapm.h>
14 #include "../common/soc-intel-quirks.h"
37 for_each_acpi_dev_match(adev, hid, NULL, -1) in get_num_codecs()
77 * According to the definition of 'DAI Sel Mux' mixer in max98373.c, rx mask
78 * should choose two channels from TDM slots, the LSB of rx mask is left channel
82 unsigned int rx; member
84 {.rx = 0x3},
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/linux/drivers/net/ethernet/ibm/emac/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Driver for PowerPC 4xx on-chip ethernet controller.
28 #include <linux/dma-mapping.h>
56 /* RX BD size for the given MTU */
65 /* Size of RX skb for the given MTU */
73 /* RX DMA sync size */
80 * - normal statistics (packet count, etc)
81 * - error statistics
89 /* Normal TX/RX Statistics */
103 /* Software RX Errors */
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/linux/include/uapi/linux/hsi/
H A Dcs-protocol.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * cmt-speech interface definitions
20 /* user-space API versioning */
23 /* APE kernel <-> user space messages */
52 /* maximum number of TX/RX buffers */
58 __u32 rx_bufs; /* number of RX buffer slots */
59 __u32 tx_bufs; /* number of TX buffer slots */
76 * This information is meant as read-only information for the application.
81 __u32 rx_bufs; /* # of RX buffers */
84 /* array of offsets within the mmap area for each RX and TX buffer */
/linux/drivers/mfd/
H A Ddln2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Diolan DLN-2 USB adapter
8 * i2c-diolan-u2c.c
9 * Copyright (c) 2010-2011 Ericsson AB
66 /* if non-NULL the URB contains the response */
76 * the echo header field to index the slots field and find the receive context
80 /* RX slots bitmap */
83 /* used to wait for a free RX slot */
86 /* used to wait for an RX operation to complete */
87 struct dln2_rx_context slots[DLN2_MAX_RX_SLOTS]; member
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/linux/sound/soc/ti/
H A Ddavinci-mcasp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
37 #include "edma-pcm.h"
38 #include "sdma-pcm.h"
39 #include "udma-pcm.h"
40 #include "davinci-mcasp.h"
134 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
141 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
148 void __iomem *reg = mcasp->base + offset; in mcasp_mod_bits()
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H A Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
30 #include "edma-pcm.h"
31 #include "davinci-i2s.h"
33 #define DRV_NAME "davinci-i2s"
38 * - This driver supports the "Audio Serial Port" (ASP),
41 * - But it labels it a "Multi-channel Buffered Serial Port"
43 * backward-compatible, possibly explaining that confusion.
45 * - OMAP chips have a controller called McBSP, which is
48 * - Newer DaVinci chips have a controller called McASP,
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/linux/sound/arm/
H A Daaci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
28 #define DRIVER_NAME "aaci-pl041"
39 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); in aaci_ac97_select_codec()
42 * Ensure that the slot 1/2 RX registers are empty. in aaci_ac97_select_codec()
44 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_select_codec()
46 readl(aaci->base + AACI_SL2RX); in aaci_ac97_select_codec()
48 readl(aaci->base + AACI_SL1RX); in aaci_ac97_select_codec()
50 if (maincr != readl(aaci->base + AACI_MAINCR)) { in aaci_ac97_select_codec()
51 writel(maincr, aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()
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/linux/sound/soc/sunxi/
H A Dsun4i-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include <sound/soc-dai.h>
85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
93 /* Defines required for sun8i-h3 support */
106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
133 /* Defines required for sun50i-h6 support */
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