12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
29aa32835SJeff Kirsher /*
33396c782SPaul Gortmaker * drivers/net/ethernet/ibm/emac/core.h
49aa32835SJeff Kirsher *
59aa32835SJeff Kirsher * Driver for PowerPC 4xx on-chip ethernet controller.
69aa32835SJeff Kirsher *
79aa32835SJeff Kirsher * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
89aa32835SJeff Kirsher * <benh@kernel.crashing.org>
99aa32835SJeff Kirsher *
109aa32835SJeff Kirsher * Based on the arch/ppc version of the driver:
119aa32835SJeff Kirsher *
129aa32835SJeff Kirsher * Copyright (c) 2004, 2005 Zultys Technologies.
139aa32835SJeff Kirsher * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
149aa32835SJeff Kirsher *
159aa32835SJeff Kirsher * Based on original work by
169aa32835SJeff Kirsher * Armin Kuster <akuster@mvista.com>
179aa32835SJeff Kirsher * Johnnie Peters <jpeters@mvista.com>
189aa32835SJeff Kirsher * Copyright 2000, 2001 MontaVista Softare Inc.
199aa32835SJeff Kirsher */
209aa32835SJeff Kirsher #ifndef __IBM_NEWEMAC_CORE_H
219aa32835SJeff Kirsher #define __IBM_NEWEMAC_CORE_H
229aa32835SJeff Kirsher
239aa32835SJeff Kirsher #include <linux/module.h>
249aa32835SJeff Kirsher #include <linux/list.h>
259aa32835SJeff Kirsher #include <linux/kernel.h>
269aa32835SJeff Kirsher #include <linux/interrupt.h>
279aa32835SJeff Kirsher #include <linux/netdevice.h>
289aa32835SJeff Kirsher #include <linux/dma-mapping.h>
299aa32835SJeff Kirsher #include <linux/spinlock.h>
309aa32835SJeff Kirsher #include <linux/slab.h>
319aa32835SJeff Kirsher
329aa32835SJeff Kirsher #include <asm/io.h>
339aa32835SJeff Kirsher #include <asm/dcr.h>
349aa32835SJeff Kirsher
359aa32835SJeff Kirsher #include "emac.h"
369aa32835SJeff Kirsher #include "phy.h"
379aa32835SJeff Kirsher #include "zmii.h"
389aa32835SJeff Kirsher #include "rgmii.h"
399aa32835SJeff Kirsher #include "mal.h"
409aa32835SJeff Kirsher #include "tah.h"
419aa32835SJeff Kirsher #include "debug.h"
429aa32835SJeff Kirsher
433b3bceefSTony Breeds #define NUM_TX_BUFF CONFIG_IBM_EMAC_TXB
443b3bceefSTony Breeds #define NUM_RX_BUFF CONFIG_IBM_EMAC_RXB
459aa32835SJeff Kirsher
469aa32835SJeff Kirsher /* Simple sanity check */
479aa32835SJeff Kirsher #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
489aa32835SJeff Kirsher #error Invalid number of buffer descriptors (greater than 256)
499aa32835SJeff Kirsher #endif
509aa32835SJeff Kirsher
519aa32835SJeff Kirsher #define EMAC_MIN_MTU 46
529aa32835SJeff Kirsher
539aa32835SJeff Kirsher /* Maximum L2 header length (VLAN tagged, no FCS) */
549aa32835SJeff Kirsher #define EMAC_MTU_OVERHEAD (6 * 2 + 2 + 4)
559aa32835SJeff Kirsher
569aa32835SJeff Kirsher /* RX BD size for the given MTU */
emac_rx_size(int mtu)579aa32835SJeff Kirsher static inline int emac_rx_size(int mtu)
589aa32835SJeff Kirsher {
599aa32835SJeff Kirsher if (mtu > ETH_DATA_LEN)
609aa32835SJeff Kirsher return MAL_MAX_RX_SIZE;
619aa32835SJeff Kirsher else
629aa32835SJeff Kirsher return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
639aa32835SJeff Kirsher }
649aa32835SJeff Kirsher
659aa32835SJeff Kirsher /* Size of RX skb for the given MTU */
emac_rx_skb_size(int mtu)669aa32835SJeff Kirsher static inline int emac_rx_skb_size(int mtu)
679aa32835SJeff Kirsher {
689aa32835SJeff Kirsher int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
6922087d65SChristian Lamparter
7022087d65SChristian Lamparter return SKB_DATA_ALIGN(size + NET_IP_ALIGN) + NET_SKB_PAD;
719aa32835SJeff Kirsher }
729aa32835SJeff Kirsher
739aa32835SJeff Kirsher /* RX DMA sync size */
emac_rx_sync_size(int mtu)749aa32835SJeff Kirsher static inline int emac_rx_sync_size(int mtu)
759aa32835SJeff Kirsher {
7622087d65SChristian Lamparter return SKB_DATA_ALIGN(emac_rx_size(mtu) + NET_IP_ALIGN);
779aa32835SJeff Kirsher }
789aa32835SJeff Kirsher
799aa32835SJeff Kirsher /* Driver statistcs is split into two parts to make it more cache friendly:
809aa32835SJeff Kirsher * - normal statistics (packet count, etc)
819aa32835SJeff Kirsher * - error statistics
829aa32835SJeff Kirsher *
839aa32835SJeff Kirsher * When statistics is requested by ethtool, these parts are concatenated,
849aa32835SJeff Kirsher * normal one goes first.
859aa32835SJeff Kirsher *
869aa32835SJeff Kirsher * Please, keep these structures in sync with emac_stats_keys.
879aa32835SJeff Kirsher */
889aa32835SJeff Kirsher
899aa32835SJeff Kirsher /* Normal TX/RX Statistics */
909aa32835SJeff Kirsher struct emac_stats {
919aa32835SJeff Kirsher u64 rx_packets;
929aa32835SJeff Kirsher u64 rx_bytes;
939aa32835SJeff Kirsher u64 tx_packets;
949aa32835SJeff Kirsher u64 tx_bytes;
959aa32835SJeff Kirsher u64 rx_packets_csum;
969aa32835SJeff Kirsher u64 tx_packets_csum;
979aa32835SJeff Kirsher };
989aa32835SJeff Kirsher
999aa32835SJeff Kirsher /* Error statistics */
1009aa32835SJeff Kirsher struct emac_error_stats {
1019aa32835SJeff Kirsher u64 tx_undo;
1029aa32835SJeff Kirsher
1039aa32835SJeff Kirsher /* Software RX Errors */
1049aa32835SJeff Kirsher u64 rx_dropped_stack;
1059aa32835SJeff Kirsher u64 rx_dropped_oom;
1069aa32835SJeff Kirsher u64 rx_dropped_error;
1079aa32835SJeff Kirsher u64 rx_dropped_resize;
1089aa32835SJeff Kirsher u64 rx_dropped_mtu;
1099aa32835SJeff Kirsher u64 rx_stopped;
1109aa32835SJeff Kirsher /* BD reported RX errors */
1119aa32835SJeff Kirsher u64 rx_bd_errors;
1129aa32835SJeff Kirsher u64 rx_bd_overrun;
1139aa32835SJeff Kirsher u64 rx_bd_bad_packet;
1149aa32835SJeff Kirsher u64 rx_bd_runt_packet;
1159aa32835SJeff Kirsher u64 rx_bd_short_event;
1169aa32835SJeff Kirsher u64 rx_bd_alignment_error;
1179aa32835SJeff Kirsher u64 rx_bd_bad_fcs;
1189aa32835SJeff Kirsher u64 rx_bd_packet_too_long;
1199aa32835SJeff Kirsher u64 rx_bd_out_of_range;
1209aa32835SJeff Kirsher u64 rx_bd_in_range;
1219aa32835SJeff Kirsher /* EMAC IRQ reported RX errors */
1229aa32835SJeff Kirsher u64 rx_parity;
1239aa32835SJeff Kirsher u64 rx_fifo_overrun;
1249aa32835SJeff Kirsher u64 rx_overrun;
1259aa32835SJeff Kirsher u64 rx_bad_packet;
1269aa32835SJeff Kirsher u64 rx_runt_packet;
1279aa32835SJeff Kirsher u64 rx_short_event;
1289aa32835SJeff Kirsher u64 rx_alignment_error;
1299aa32835SJeff Kirsher u64 rx_bad_fcs;
1309aa32835SJeff Kirsher u64 rx_packet_too_long;
1319aa32835SJeff Kirsher u64 rx_out_of_range;
1329aa32835SJeff Kirsher u64 rx_in_range;
1339aa32835SJeff Kirsher
1349aa32835SJeff Kirsher /* Software TX Errors */
1359aa32835SJeff Kirsher u64 tx_dropped;
1369aa32835SJeff Kirsher /* BD reported TX errors */
1379aa32835SJeff Kirsher u64 tx_bd_errors;
1389aa32835SJeff Kirsher u64 tx_bd_bad_fcs;
1399aa32835SJeff Kirsher u64 tx_bd_carrier_loss;
1409aa32835SJeff Kirsher u64 tx_bd_excessive_deferral;
1419aa32835SJeff Kirsher u64 tx_bd_excessive_collisions;
1429aa32835SJeff Kirsher u64 tx_bd_late_collision;
1439aa32835SJeff Kirsher u64 tx_bd_multple_collisions;
1449aa32835SJeff Kirsher u64 tx_bd_single_collision;
1459aa32835SJeff Kirsher u64 tx_bd_underrun;
1469aa32835SJeff Kirsher u64 tx_bd_sqe;
1479aa32835SJeff Kirsher /* EMAC IRQ reported TX errors */
1489aa32835SJeff Kirsher u64 tx_parity;
1499aa32835SJeff Kirsher u64 tx_underrun;
1509aa32835SJeff Kirsher u64 tx_sqe;
1519aa32835SJeff Kirsher u64 tx_errors;
1529aa32835SJeff Kirsher };
1539aa32835SJeff Kirsher
1549aa32835SJeff Kirsher #define EMAC_ETHTOOL_STATS_COUNT ((sizeof(struct emac_stats) + \
1559aa32835SJeff Kirsher sizeof(struct emac_error_stats)) \
1569aa32835SJeff Kirsher / sizeof(u64))
1579aa32835SJeff Kirsher
1589aa32835SJeff Kirsher struct emac_instance {
1599aa32835SJeff Kirsher struct net_device *ndev;
1609aa32835SJeff Kirsher struct emac_regs __iomem *emacp;
1619aa32835SJeff Kirsher struct platform_device *ofdev;
1629aa32835SJeff Kirsher struct device_node **blist; /* bootlist entry */
1639aa32835SJeff Kirsher
1649aa32835SJeff Kirsher /* MAL linkage */
1659aa32835SJeff Kirsher u32 mal_ph;
1669aa32835SJeff Kirsher struct platform_device *mal_dev;
1679aa32835SJeff Kirsher u32 mal_rx_chan;
1689aa32835SJeff Kirsher u32 mal_tx_chan;
1699aa32835SJeff Kirsher struct mal_instance *mal;
1709aa32835SJeff Kirsher struct mal_commac commac;
1719aa32835SJeff Kirsher
1729aa32835SJeff Kirsher /* PHY infos */
173f9218617SAndrew Lunn phy_interface_t phy_mode;
1749aa32835SJeff Kirsher u32 phy_map;
1759aa32835SJeff Kirsher u32 phy_address;
1769aa32835SJeff Kirsher u32 phy_feat_exc;
1779aa32835SJeff Kirsher struct mii_phy phy;
1789aa32835SJeff Kirsher struct mutex link_lock;
1799aa32835SJeff Kirsher struct delayed_work link_work;
1809aa32835SJeff Kirsher int link_polling;
1819aa32835SJeff Kirsher
1829aa32835SJeff Kirsher /* GPCS PHY infos */
1839aa32835SJeff Kirsher u32 gpcs_address;
1849aa32835SJeff Kirsher
1859aa32835SJeff Kirsher /* Shared MDIO if any */
1869aa32835SJeff Kirsher u32 mdio_ph;
1879aa32835SJeff Kirsher struct platform_device *mdio_dev;
1889aa32835SJeff Kirsher struct emac_instance *mdio_instance;
1899aa32835SJeff Kirsher struct mutex mdio_lock;
1909aa32835SJeff Kirsher
1919aa32835SJeff Kirsher /* ZMII infos if any */
1929aa32835SJeff Kirsher u32 zmii_ph;
1939aa32835SJeff Kirsher u32 zmii_port;
1949aa32835SJeff Kirsher struct platform_device *zmii_dev;
1959aa32835SJeff Kirsher
1969aa32835SJeff Kirsher /* RGMII infos if any */
1979aa32835SJeff Kirsher u32 rgmii_ph;
1989aa32835SJeff Kirsher u32 rgmii_port;
1999aa32835SJeff Kirsher struct platform_device *rgmii_dev;
2009aa32835SJeff Kirsher
2019aa32835SJeff Kirsher /* TAH infos if any */
2029aa32835SJeff Kirsher u32 tah_ph;
2039aa32835SJeff Kirsher u32 tah_port;
2049aa32835SJeff Kirsher struct platform_device *tah_dev;
2059aa32835SJeff Kirsher
2069aa32835SJeff Kirsher /* IRQs */
2079aa32835SJeff Kirsher int wol_irq;
2089aa32835SJeff Kirsher int emac_irq;
2099aa32835SJeff Kirsher
2109aa32835SJeff Kirsher /* OPB bus frequency in Mhz */
2119aa32835SJeff Kirsher u32 opb_bus_freq;
2129aa32835SJeff Kirsher
2139aa32835SJeff Kirsher /* Cell index within an ASIC (for clk mgmnt) */
2149aa32835SJeff Kirsher u32 cell_index;
2159aa32835SJeff Kirsher
2169aa32835SJeff Kirsher /* Max supported MTU */
2179aa32835SJeff Kirsher u32 max_mtu;
2189aa32835SJeff Kirsher
2199aa32835SJeff Kirsher /* Feature bits (from probe table) */
2209aa32835SJeff Kirsher unsigned int features;
2219aa32835SJeff Kirsher
2229aa32835SJeff Kirsher /* Tx and Rx fifo sizes & other infos in bytes */
2239aa32835SJeff Kirsher u32 tx_fifo_size;
2249aa32835SJeff Kirsher u32 tx_fifo_size_gige;
2259aa32835SJeff Kirsher u32 rx_fifo_size;
2269aa32835SJeff Kirsher u32 rx_fifo_size_gige;
2279aa32835SJeff Kirsher u32 fifo_entry_size;
2289aa32835SJeff Kirsher u32 mal_burst_size; /* move to MAL ? */
2299aa32835SJeff Kirsher
2309aa32835SJeff Kirsher /* IAHT and GAHT filter parameterization */
2319aa32835SJeff Kirsher u32 xaht_slots_shift;
2329aa32835SJeff Kirsher u32 xaht_width_shift;
2339aa32835SJeff Kirsher
2349aa32835SJeff Kirsher /* Descriptor management
2359aa32835SJeff Kirsher */
2369aa32835SJeff Kirsher struct mal_descriptor *tx_desc;
2379aa32835SJeff Kirsher int tx_cnt;
2389aa32835SJeff Kirsher int tx_slot;
2399aa32835SJeff Kirsher int ack_slot;
2409aa32835SJeff Kirsher
2419aa32835SJeff Kirsher struct mal_descriptor *rx_desc;
2429aa32835SJeff Kirsher int rx_slot;
2439aa32835SJeff Kirsher struct sk_buff *rx_sg_skb; /* 1 */
2449aa32835SJeff Kirsher int rx_skb_size;
2459aa32835SJeff Kirsher int rx_sync_size;
2469aa32835SJeff Kirsher
2479aa32835SJeff Kirsher struct sk_buff *tx_skb[NUM_TX_BUFF];
2489aa32835SJeff Kirsher struct sk_buff *rx_skb[NUM_RX_BUFF];
2499aa32835SJeff Kirsher
2509aa32835SJeff Kirsher /* Stats
2519aa32835SJeff Kirsher */
2529aa32835SJeff Kirsher struct emac_error_stats estats;
2539aa32835SJeff Kirsher struct emac_stats stats;
2549aa32835SJeff Kirsher
2559aa32835SJeff Kirsher /* Misc
2569aa32835SJeff Kirsher */
2579aa32835SJeff Kirsher int reset_failed;
2589aa32835SJeff Kirsher int stop_timeout; /* in us */
2599aa32835SJeff Kirsher int no_mcast;
2609aa32835SJeff Kirsher int mcast_pending;
2619aa32835SJeff Kirsher int opened;
2629aa32835SJeff Kirsher struct work_struct reset_work;
2639aa32835SJeff Kirsher spinlock_t lock;
2649aa32835SJeff Kirsher };
2659aa32835SJeff Kirsher
2669aa32835SJeff Kirsher /*
2679aa32835SJeff Kirsher * Features of various EMAC implementations
2689aa32835SJeff Kirsher */
2699aa32835SJeff Kirsher
2709aa32835SJeff Kirsher /*
2719aa32835SJeff Kirsher * No flow control on 40x according to the original driver
2729aa32835SJeff Kirsher */
2739aa32835SJeff Kirsher #define EMAC_FTR_NO_FLOW_CONTROL_40x 0x00000001
2749aa32835SJeff Kirsher /*
2759aa32835SJeff Kirsher * Cell is an EMAC4
2769aa32835SJeff Kirsher */
2779aa32835SJeff Kirsher #define EMAC_FTR_EMAC4 0x00000002
2789aa32835SJeff Kirsher /*
2799aa32835SJeff Kirsher * For the 440SPe, AMCC inexplicably changed the polarity of
2809aa32835SJeff Kirsher * the "operation complete" bit in the MII control register.
2819aa32835SJeff Kirsher */
2829aa32835SJeff Kirsher #define EMAC_FTR_STACR_OC_INVERT 0x00000004
2839aa32835SJeff Kirsher /*
2849aa32835SJeff Kirsher * Set if we have a TAH.
2859aa32835SJeff Kirsher */
2869aa32835SJeff Kirsher #define EMAC_FTR_HAS_TAH 0x00000008
2879aa32835SJeff Kirsher /*
2889aa32835SJeff Kirsher * Set if we have a ZMII.
2899aa32835SJeff Kirsher */
2909aa32835SJeff Kirsher #define EMAC_FTR_HAS_ZMII 0x00000010
2919aa32835SJeff Kirsher /*
2929aa32835SJeff Kirsher * Set if we have a RGMII.
2939aa32835SJeff Kirsher */
2949aa32835SJeff Kirsher #define EMAC_FTR_HAS_RGMII 0x00000020
2959aa32835SJeff Kirsher /*
2969aa32835SJeff Kirsher * Set if we have new type STACR with STAOPC
2979aa32835SJeff Kirsher */
2989aa32835SJeff Kirsher #define EMAC_FTR_HAS_NEW_STACR 0x00000040
2999aa32835SJeff Kirsher /*
3009aa32835SJeff Kirsher * Set if we need phy clock workaround for 440gx
3019aa32835SJeff Kirsher */
3029aa32835SJeff Kirsher #define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080
3039aa32835SJeff Kirsher /*
3049aa32835SJeff Kirsher * Set if we need phy clock workaround for 440ep or 440gr
3059aa32835SJeff Kirsher */
3069aa32835SJeff Kirsher #define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100
3079aa32835SJeff Kirsher /*
3089aa32835SJeff Kirsher * The 405EX and 460EX contain the EMAC4SYNC core
3099aa32835SJeff Kirsher */
3109aa32835SJeff Kirsher #define EMAC_FTR_EMAC4SYNC 0x00000200
3119aa32835SJeff Kirsher /*
3129aa32835SJeff Kirsher * Set if we need phy clock workaround for 460ex or 460gt
3139aa32835SJeff Kirsher */
3149aa32835SJeff Kirsher #define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400
315ae5d3372SDuc Dang /*
316ae5d3372SDuc Dang * APM821xx requires Jumbo frame size set explicitly
317ae5d3372SDuc Dang */
318ae5d3372SDuc Dang #define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE 0x00000800
319ae5d3372SDuc Dang /*
320ae5d3372SDuc Dang * APM821xx does not support Half Duplex mode
321ae5d3372SDuc Dang */
322ae5d3372SDuc Dang #define EMAC_FTR_APM821XX_NO_HALF_DUPLEX 0x00001000
3239aa32835SJeff Kirsher
3249aa32835SJeff Kirsher /* Right now, we don't quite handle the always/possible masks on the
3259aa32835SJeff Kirsher * most optimal way as we don't have a way to say something like
3269aa32835SJeff Kirsher * always EMAC4. Patches welcome.
3279aa32835SJeff Kirsher */
3289aa32835SJeff Kirsher enum {
3299aa32835SJeff Kirsher EMAC_FTRS_ALWAYS = 0,
3309aa32835SJeff Kirsher
3319aa32835SJeff Kirsher EMAC_FTRS_POSSIBLE =
3323b3bceefSTony Breeds #ifdef CONFIG_IBM_EMAC_EMAC4
3339aa32835SJeff Kirsher EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC |
3349aa32835SJeff Kirsher EMAC_FTR_HAS_NEW_STACR |
3359aa32835SJeff Kirsher EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
3369aa32835SJeff Kirsher #endif
3373b3bceefSTony Breeds #ifdef CONFIG_IBM_EMAC_TAH
3389aa32835SJeff Kirsher EMAC_FTR_HAS_TAH |
3399aa32835SJeff Kirsher #endif
3403b3bceefSTony Breeds #ifdef CONFIG_IBM_EMAC_ZMII
3419aa32835SJeff Kirsher EMAC_FTR_HAS_ZMII |
3429aa32835SJeff Kirsher #endif
3433b3bceefSTony Breeds #ifdef CONFIG_IBM_EMAC_RGMII
3449aa32835SJeff Kirsher EMAC_FTR_HAS_RGMII |
3459aa32835SJeff Kirsher #endif
3463b3bceefSTony Breeds #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
3479aa32835SJeff Kirsher EMAC_FTR_NO_FLOW_CONTROL_40x |
3489aa32835SJeff Kirsher #endif
3499aa32835SJeff Kirsher EMAC_FTR_460EX_PHY_CLK_FIX |
350ae5d3372SDuc Dang EMAC_FTR_440EP_PHY_CLK_FIX |
351ae5d3372SDuc Dang EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
352ae5d3372SDuc Dang EMAC_FTR_APM821XX_NO_HALF_DUPLEX,
3539aa32835SJeff Kirsher };
3549aa32835SJeff Kirsher
emac_has_feature(struct emac_instance * dev,unsigned long feature)3559aa32835SJeff Kirsher static inline int emac_has_feature(struct emac_instance *dev,
3569aa32835SJeff Kirsher unsigned long feature)
3579aa32835SJeff Kirsher {
3589aa32835SJeff Kirsher return (EMAC_FTRS_ALWAYS & feature) ||
3599aa32835SJeff Kirsher (EMAC_FTRS_POSSIBLE & dev->features & feature);
3609aa32835SJeff Kirsher }
3619aa32835SJeff Kirsher
3629aa32835SJeff Kirsher /*
3639aa32835SJeff Kirsher * Various instances of the EMAC core have varying 1) number of
3649aa32835SJeff Kirsher * address match slots, 2) width of the registers for handling address
3659aa32835SJeff Kirsher * match slots, 3) number of registers for handling address match
3669aa32835SJeff Kirsher * slots and 4) base offset for those registers.
3679aa32835SJeff Kirsher *
3689aa32835SJeff Kirsher * These macros and inlines handle these differences based on
3699aa32835SJeff Kirsher * parameters supplied by the device structure which are, in turn,
3709aa32835SJeff Kirsher * initialized based on the "compatible" entry in the device tree.
3719aa32835SJeff Kirsher */
3729aa32835SJeff Kirsher
3739aa32835SJeff Kirsher #define EMAC4_XAHT_SLOTS_SHIFT 6
3749aa32835SJeff Kirsher #define EMAC4_XAHT_WIDTH_SHIFT 4
3759aa32835SJeff Kirsher
3769aa32835SJeff Kirsher #define EMAC4SYNC_XAHT_SLOTS_SHIFT 8
3779aa32835SJeff Kirsher #define EMAC4SYNC_XAHT_WIDTH_SHIFT 5
3789aa32835SJeff Kirsher
379ee4fccbeSKees Cook /* The largest span between slots and widths above is 3 */
380ee4fccbeSKees Cook #define EMAC_XAHT_MAX_REGS (1 << 3)
381ee4fccbeSKees Cook
3829aa32835SJeff Kirsher #define EMAC_XAHT_SLOTS(dev) (1 << (dev)->xaht_slots_shift)
3839aa32835SJeff Kirsher #define EMAC_XAHT_WIDTH(dev) (1 << (dev)->xaht_width_shift)
3849aa32835SJeff Kirsher #define EMAC_XAHT_REGS(dev) (1 << ((dev)->xaht_slots_shift - \
3859aa32835SJeff Kirsher (dev)->xaht_width_shift))
3869aa32835SJeff Kirsher
3879aa32835SJeff Kirsher #define EMAC_XAHT_CRC_TO_SLOT(dev, crc) \
3889aa32835SJeff Kirsher ((EMAC_XAHT_SLOTS(dev) - 1) - \
3899aa32835SJeff Kirsher ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) - \
3909aa32835SJeff Kirsher (dev)->xaht_slots_shift)))
3919aa32835SJeff Kirsher
3929aa32835SJeff Kirsher #define EMAC_XAHT_SLOT_TO_REG(dev, slot) \
3939aa32835SJeff Kirsher ((slot) >> (dev)->xaht_width_shift)
3949aa32835SJeff Kirsher
3959aa32835SJeff Kirsher #define EMAC_XAHT_SLOT_TO_MASK(dev, slot) \
3969aa32835SJeff Kirsher ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >> \
3979aa32835SJeff Kirsher ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))
3989aa32835SJeff Kirsher
emac_xaht_base(struct emac_instance * dev)399*5aa3b55bSSimon Horman static inline u32 __iomem *emac_xaht_base(struct emac_instance *dev)
4009aa32835SJeff Kirsher {
4019aa32835SJeff Kirsher struct emac_regs __iomem *p = dev->emacp;
4029aa32835SJeff Kirsher int offset;
4039aa32835SJeff Kirsher
4049aa32835SJeff Kirsher /* The first IAHT entry always is the base of the block of
4059aa32835SJeff Kirsher * IAHT and GAHT registers.
4069aa32835SJeff Kirsher */
4079aa32835SJeff Kirsher if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
4089aa32835SJeff Kirsher offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
4099aa32835SJeff Kirsher else
4109aa32835SJeff Kirsher offset = offsetof(struct emac_regs, u0.emac4.iaht1);
4119aa32835SJeff Kirsher
412*5aa3b55bSSimon Horman return (u32 __iomem *)((__force ptrdiff_t)p + offset);
4139aa32835SJeff Kirsher }
4149aa32835SJeff Kirsher
emac_gaht_base(struct emac_instance * dev)415*5aa3b55bSSimon Horman static inline u32 __iomem *emac_gaht_base(struct emac_instance *dev)
4169aa32835SJeff Kirsher {
4179aa32835SJeff Kirsher /* GAHT registers always come after an identical number of
4189aa32835SJeff Kirsher * IAHT registers.
4199aa32835SJeff Kirsher */
4209aa32835SJeff Kirsher return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev);
4219aa32835SJeff Kirsher }
4229aa32835SJeff Kirsher
emac_iaht_base(struct emac_instance * dev)4239aa32835SJeff Kirsher static inline u32 *emac_iaht_base(struct emac_instance *dev)
4249aa32835SJeff Kirsher {
4259aa32835SJeff Kirsher /* IAHT registers always come before an identical number of
4269aa32835SJeff Kirsher * GAHT registers.
4279aa32835SJeff Kirsher */
4289aa32835SJeff Kirsher return emac_xaht_base(dev);
4299aa32835SJeff Kirsher }
4309aa32835SJeff Kirsher
4319aa32835SJeff Kirsher /* Ethtool get_regs complex data.
4329aa32835SJeff Kirsher * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
4339aa32835SJeff Kirsher * when available.
4349aa32835SJeff Kirsher *
4359aa32835SJeff Kirsher * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
4369aa32835SJeff Kirsher * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
4379aa32835SJeff Kirsher * Each register component is preceded with emac_ethtool_regs_subhdr.
4389aa32835SJeff Kirsher * Order of the optional headers follows their relative bit posititions
4399aa32835SJeff Kirsher * in emac_ethtool_regs_hdr.components
4409aa32835SJeff Kirsher */
4419aa32835SJeff Kirsher #define EMAC_ETHTOOL_REGS_ZMII 0x00000001
4429aa32835SJeff Kirsher #define EMAC_ETHTOOL_REGS_RGMII 0x00000002
4439aa32835SJeff Kirsher #define EMAC_ETHTOOL_REGS_TAH 0x00000004
4449aa32835SJeff Kirsher
4459aa32835SJeff Kirsher struct emac_ethtool_regs_hdr {
4469aa32835SJeff Kirsher u32 components;
4479aa32835SJeff Kirsher };
4489aa32835SJeff Kirsher
4499aa32835SJeff Kirsher struct emac_ethtool_regs_subhdr {
4509aa32835SJeff Kirsher u32 version;
4519aa32835SJeff Kirsher u32 index;
4529aa32835SJeff Kirsher };
4539aa32835SJeff Kirsher
454661dfc65SIvan Mikhaylov #define EMAC_ETHTOOL_REGS_VER 3
455661dfc65SIvan Mikhaylov #define EMAC4_ETHTOOL_REGS_VER 4
456661dfc65SIvan Mikhaylov #define EMAC4SYNC_ETHTOOL_REGS_VER 5
4579aa32835SJeff Kirsher
4589aa32835SJeff Kirsher #endif /* __IBM_NEWEMAC_CORE_H */
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