| /linux/Documentation/devicetree/bindings/net/ |
| H A D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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| /linux/drivers/net/ethernet/freescale/fman/ |
| H A D | fman_memac.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
24 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
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| /linux/drivers/net/ethernet/sun/ |
| H A D | cassini.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
82 RX completion reg updated.
86 RX Kick == RX complete */
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| /linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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| /linux/drivers/phy/ti/ |
| H A D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
131 u16 m; member
180 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
305 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
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| /linux/drivers/net/ethernet/sfc/ |
| H A D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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| /linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_defines.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
135 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
138 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
139 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
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| /linux/drivers/net/ethernet/chelsio/cxgb/ |
| H A D | vsc7326_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
9 * PD0011-01-14-Meigs-II 2002-12-12
69 * fn = FIFO number, 0-9
84 * bn = bucket number 0-10 (yes, 11 buckets)
114 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
133 * tri-speed are only defined with the version that needs a port number.
140 /* 10GbE specific, and different from tri-speed */
144 #define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */
147 #define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */
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| /linux/Documentation/networking/device_drivers/ethernet/cirrus/ |
| H A D | cs89x0.rst | 1 .. SPDX-License-Identifier: GPL-2.0
33 2.1 CS8900-based Adapter Configuration
34 2.2 CS8920-based Adapter Configuration
41 4.3 Compiling the driver to support Rx DMA
46 5.2.1 Diagnostic Self-Test
66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow
67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus
69 in 16-bit ISA or EISA bus expansion slots and are available in
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
73 CS8920-based adapters are similar to the CS8900-based adapter with additional
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| /linux/drivers/net/ethernet/intel/e1000/ |
| H A D | e1000_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
511 __le32 mrq; /* Multiple Rx Queues */
529 /* Receive Descriptor - Packet Split */
537 __le32 mrq; /* Multiple Rx Queues */
553 __le16 length[3]; /* length of buffers 1-3 */
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| /linux/drivers/net/dsa/ |
| H A D | mt7530.c | 1 // SPDX-License-Identifier: GPL-2.0-only
28 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) in pcs_to_mt753x_pcs() argument
30 return container_of(pcs, struct mt753x_pcs, pcs); in pcs_to_mt753x_pcs()
49 if (priv->bus) in mt7530_mutex_lock()
50 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
56 if (priv->bus) in mt7530_mutex_unlock()
57 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
63 struct mii_bus *bus = priv->bus; in core_write()
69 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
75 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
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| /linux/drivers/scsi/bfa/ |
| H A D | bfa_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
72 #define bfa_mfg_increment_wwn_mac(m, i) \ argument
74 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
75 (u32)(m)[2]; \
77 (m)[0] = (t >> 16) & 0xFF; \
78 (m)[1] = (t >> 8) & 0xFF; \
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx95-19x19-evk.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/pwm/pwm.h>
9 #include <dt-bindings/usb/pd.h>
15 #define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */
16 #define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */
17 #define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */
18 #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */
19 #define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */
23 compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
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| /linux/drivers/net/dsa/realtek/ |
| H A D | rtl8365mb.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
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| /linux/drivers/phy/samsung/ |
| H A D | phy-exynos5-usbdrd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
253 /* Exynos9 - GS101 */
297 /* PCS registers */
363 #define PHY_TUNING_ENTRY_PHY(o, m, v) { \ argument
365 .mask = (m), \
370 #define PHY_TUNING_ENTRY_PCS(o, m, v) { \ argument
372 .mask = (m), \
377 #define PHY_TUNING_ENTRY_PMA(o, m, v) { \ argument
379 .mask = (m), \
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| /linux/drivers/net/ethernet/mscc/ |
| H A D | ocelot.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
30 /* Caller must hold &ocelot->mact_lock */
36 /* Caller must hold &ocelot->mact_lock */
48 /* Caller must hold &ocelot->mact_lock */
90 if (mc_ports & BIT(ocelot->num_phys_ports)) in __ocelot_mact_learn()
109 mutex_lock(&ocelot->mact_lock); in ocelot_mact_learn()
111 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_learn()
122 mutex_lock(&ocelot->mact_lock); in ocelot_mact_forget()
133 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_forget()
145 mutex_lock(&ocelot->mact_lock); in ocelot_mact_lookup()
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| /linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | anx7625.c | 1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
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| /linux/Documentation/admin-guide/media/ |
| H A D | bttv.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ----------------------
12 ./scripts/config -e PCI
13 ./scripts/config -m I2C
14 ./scripts/config -m INPUT
15 ./scripts/config -m MEDIA_SUPPORT
16 ./scripts/config -e MEDIA_PCI_SUPPORT
17 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
18 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
19 ./scripts/config -e MEDIA_RADIO_SUPPORT
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| /linux/drivers/net/ethernet/sfc/siena/ |
| H A D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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| /linux/drivers/net/ethernet/amd/xgbe/ |
| H A D | xgbe-mdio.c | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
18 #include "xgbe-common.h"
23 if (!pdata->phy_if.phy_impl.module_eeprom) in xgbe_phy_module_eeprom()
24 return -ENXIO; in xgbe_phy_module_eeprom()
26 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data); in xgbe_phy_module_eeprom()
32 if (!pdata->phy_if.phy_impl.module_info) in xgbe_phy_module_info()
33 return -ENXIO; in xgbe_phy_module_info()
35 return pdata->phy_if.phy_impl.module_info(pdata, modinfo); in xgbe_phy_module_info()
90 switch (pdata->an_mode) { in xgbe_an_enable_interrupts()
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
7 M: *Mail* patches to: FullName <address@domain>
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
71 M: Steffen Klassert <klassert@kernel.org>
78 M: David Dillow <dave@thedillows.org>
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| /linux/drivers/net/phy/ |
| H A D | micrel.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
129 * The value is calculated as following: (1/1000000)/((2^-32)/4)
135 * The value is calculated as following: (1/1000000)/((2^-32)/8)
420 /* Lock for Rx ts fifo */
560 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
564 if (type && type->interrupt_level_mask) in kszphy_config_intr()
565 mask = type->interrupt_level_mask; in kszphy_config_intr()
577 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in kszphy_config_intr()
640 return -EINVAL; in kszphy_setup_led()
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
28 "s0ix-enabled",
33 #define E1000_STAT(str, m) { \ argument
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
37 .stat_offset = offsetof(struct e1000_adapter, m) }
38 #define E1000_NETDEV_STAT(str, m) { \ argument
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
42 .stat_offset = offsetof(struct rtnl_link_stats64, m) }
115 struct e1000_hw *hw = &adapter->hw; in e1000_get_link_ksettings()
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| /linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_link.c | 1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
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| /linux/drivers/net/ethernet/mediatek/ |
| H A D | mtk_eth_soc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
35 static int mtk_msg_level = -1;
37 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
291 __raw_writel(val, eth->base + reg); in mtk_w32()
296 return __raw_readl(eth->base + reg); in mtk_r32()
322 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
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