/linux/Documentation/devicetree/bindings/usb/ |
H A D | snps,dwc3-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Felipe Balbi <balbi@kernel.org> 14 vendor-specific implementation or as a standalone component. 17 - $ref: usb-drd.yaml# 18 - if: 24 - dr_mode 28 $ref: usb-xhci.yaml# [all …]
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H A D | chipidea,usb2-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Xu Yang <xu.yang_2@nxp.com> 25 clock-names: 31 power-domains: 37 reset-names: 40 "#reset-cells": 48 itc-setting: [all …]
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/linux/Documentation/devicetree/bindings/dma/ |
H A D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers 7 - compatible: must be one of 17 - #dma-cells: must be 2: the first integer is a terminal number, to which this 26 - max-burst-mem-read: limit burst size for memory reads 28 than using the maximum burst size allowed by the hardware's buffer size. 29 - max-burst-mem-write: limit burst size for memory writes 31 than using the maximum burst size allowed by the hardware's buffer size. 32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM 35 You can use dma-channels and dma-requests as described in dma.txt, although they 40 dma: dma-controller@48000000 { [all …]
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H A D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC) 4 - compatible: Must be "img,pistachio-mdc-dma". 5 - reg: Must contain the base address and length of the MDC registers. 6 - interrupts: Must contain all the per-channel DMA interrupts. 7 - clocks: Must contain an entry for each entry in clock-names. 8 See ../clock/clock-bindings.txt for details. 9 - clock-names: Must include the following entries: 10 - sys: MDC system interface clock. 11 - img,cr-periph: Must contain a phandle to the peripheral control syscon 13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier. [all …]
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/linux/drivers/net/ethernet/broadcom/ |
H A D | bcm63xx_enet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 19 /* maximum burst len for dma (4 bytes unit) */ 24 * must be low enough so that a DMA transfer of above burst length can 29 * hardware maximum rx/tx packet size including FCS, max mtu is 30 * actually 2047, but if we set max rx size register to 2047 we won't 204 /* hw view of rx & tx dma ring */ 208 /* allocated size (in bytes) for rx & tx dma ring */ 215 /* dma channel id for rx */ 218 /* number of dma desc in rx ring */ 221 /* cpu view of rx dma ring */ [all …]
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H A D | bcm4908_enet.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 59 #define ENET_DMA_CH0_CFG 0xa00 /* RX */ 61 #define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */ 67 #define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */ 74 #define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
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H A D | b44.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */ 43 #define ISTAT_RX 0x00010000 /* RX Interrupt */ 56 #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */ 57 #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */ 94 #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */ 98 #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */ 99 #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */ 100 #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */ 126 #define B44_RXCONFIG 0x0400UL /* EMAC RX Config */ [all …]
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/linux/Documentation/networking/ |
H A D | pktgen.rst | 1 .. SPDX-License-Identifier: GPL-2.0 7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel 27 Tuning NIC for max performance 31 overload type of benchmarking, as this could hurt the normal use-case. 35 # ethtool -G ethX tx 1024 44 ring-buffers for various performance reasons, and packets stalling 48 (Intel 82599 chip). This driver (ixgbe) combines TX+RX ring cleanups, 49 and the cleanup interval is affected by the ethtool --coalesce setting 50 of parameter "rx-usecs". 54 # ethtool -C ethX rx-usecs 30 [all …]
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/linux/Documentation/devicetree/bindings/net/ |
H A D | ibm,emac.txt | 8 correct clock-frequency property. 13 - device_type : "network" 15 - compatible : compatible list, contains 2 entries, first is 16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, 18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", 20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> 21 - reg : <registers mapping> 22 - local-mac-address : 6 bytes, MAC address 23 - mal-device : phandle of the associated McMAL node 24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated [all …]
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/linux/include/linux/phy/ |
H A D | phy-mipi-dphy.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set 13 * MIPI D-PHY phy. 20 * Clock transitions and disable the Clock Lane HS-RX. 53 * Lane LP-00 Line state immediately before the HS-0 Line 86 * Time, in picoseconds, that the transmitter drives the HS-0 88 * burst. 97 * Time, in picoseconds, that the transmitter drives the HS-0 116 * of @hs_trail or @clk_trail, to the start of the LP- 11 117 * state following a HS burst. [all …]
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/linux/drivers/net/wireless/ath/wil6210/ |
H A D | interrupt.c | 1 // SPDX-License-Identifier: ISC 3 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 15 * There is ISR pseudo-cause register, 16 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE 18 * TX, RX, and MISC. 48 /* configure to Clear-On-Read mode */ 56 /* configure to Write-1-to-Clear mode */ 122 clear_bit(wil_status_irqen, wil->status); in wil6210_mask_irq_pseudo() 139 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0; in wil6210_unmask_irq_rx() [all …]
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H A D | wmi.h | 1 /* SPDX-License-Identifier: ISC */ 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2006-2012 Wilocity 70 * Each ID maps to a bit in a 32-bit bitmask value provided by the FW to 444 * - WMI_RX_MGMT_PACKET_EVENTID - for every probe resp. 445 * - WMI_SCAN_COMPLETE_EVENTID 461 /* Max duration in the home channel(ms) */ 470 * 0 - 58320 MHz 471 * 1 - 60480 MHz [all …]
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/linux/arch/arm64/boot/dts/xilinx/ |
H A D | zynqmp-zc1232-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2017 - 2021, Xilinx, Inc. 10 /dts-v1/; 13 #include "zynqmp-clk-ccf.dtsi" 17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; 27 stdout-path = "serial0:115200n8"; 43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 44 #address-cells = <1>; 45 #size-cells = <1>; 47 spi-tx-bus-width = <4>; [all …]
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H A D | zynqmp-zc1751-xm015-dc1.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 /dts-v1/; 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 20 model = "ZynqMP zc1751-xm015-dc1 RevA"; [all …]
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/linux/drivers/net/ethernet/sun/ |
H A D | sungem.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 26 #define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */ 29 #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */ 31 #define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */ 33 * after infinite burst (Apple) */ 34 #define GREG_CFG_ENBUG2FIX 0x00001000 /* Fix Rx hang after overflow */ 39 * This auto-clearing does not occur when the alias at GREG_STAT2 48 #define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */ 49 #define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */ 50 #define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */ [all …]
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/linux/drivers/spi/ |
H A D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 11 #include <linux/dma-mapping.h> 30 #include <linux/dma/imx-dma.h> 115 void (*rx)(struct spi_imx_data *spi_imx); member 138 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi() 143 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi() 148 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi() 153 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi() 159 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ [all …]
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H A D | spi-meson-spicc.c | 7 * SPDX-License-Identifier: GPL-2.0+ 12 #include <linux/clk-provider.h> 24 #include <linux/dma-mapping.h> 31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made 32 * up of one or more DMA bursts. The DMA burst implementation mechanism is, 34 * reading threshold, SPICC starts a reading DMA burst, which reads the preset 36 * For RX, when the number of words in RXFIFO is greater than the preset 37 * writing threshold, SPICC starts a writing request burst, which reads the 38 * preset number of words from RXFIFO, then write them into RX buffer. 40 * - 64 bits per word [all …]
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/ |
H A D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+ 13 - In This Release 14 - Feature List 15 - Kernel Configuration 16 - Command Line Parameters 17 - Driver Information and Notes 18 - Debug Information 19 - Support 33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0 35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores [all …]
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/linux/drivers/scsi/mvsas/ |
H A D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 28 /* driver compile-time configuration */ 30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */ 31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */ 32 /* software requires power-of-2 44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2, 49 MVS_MAX_PHYS = 8, /* max. possible phys */ 50 MVS_MAX_PORTS = 8, /* max. possible ports */ 53 MVS_MAX_DEVICES = 1024, /* max supported device */ [all …]
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/linux/drivers/net/usb/ |
H A D | smsc95xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 * Copyright (C) 2007-2008 SMSC 22 /* Rx status word */ 38 /* SCSRs - System Control and Status Registers */ 54 #define INT_STS_RX_STOP_ (0x00010000) /* RX Stopped */ 59 #define INT_STS_RXDF_ (0x00000800) /* RX Dropped Frame */ 77 #define HW_CFG_RXDOFF_ (0x00000600) /* RX Data Offset */ 80 #define HW_CFG_DRP_ (0x00000040) /* Discard Errored RX Frame */ 85 #define HW_CFG_BCE_ (0x00000002) /* Burst Cap Enable */ 90 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */ [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | am335x-nano.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/ 5 /dts-v1/; 15 cpu0-supply = <&dcdc2_reg>; 25 compatible = "gpio-leds"; 30 default-state = "off"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&misc_pins>; 39 misc_pins: misc-pins { 40 pinctrl-single,pins = < [all …]
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/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3xxx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/soc/rockchip,boot-mode.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 15 interrupt-parent = <&gic>; 37 compatible = "fixed-clock"; 38 clock-frequency = <24000000>; 39 #clock-cells = <0>; [all …]
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H A D | rv1126.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rockchip,rv1126-cru.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rockchip,rv1126-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 15 #address-cells = <1>; 16 #size-cells = <1>; [all …]
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/linux/drivers/net/wireless/ralink/rt2x00/ |
H A D | rt2x00queue.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 41 * @QID_RX: RX queue 62 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX 91 * of the scope of the skb->data pointer. 93 * @skb_dma: (PCI-only) the DMA address associated with the sk buffer. 112 * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff. 119 return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data; in get_skb_frame_desc() 131 * @RXDONE_L2PAD: 802.11 payload has been padded to 4-byte boundary. 144 * RXDONE_SIGNAL_MASK - Define to mask off all &rxdone_entry_desc_flags flags [all …]
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/linux/drivers/net/wireless/ti/wl1251/ |
H A D | reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Copyright (c) 1998-2007 Texas Instruments Incorporated 98 Host Interrupt Mask Register - 32bit (RW) 99 ------------------------------------------ 102 0 - RX0 - Rx first dubble buffer Data Interrupt 103 1 - TXD - Tx Data Interrupt 104 2 - TXXFR - Tx Transfer Interrupt 105 3 - RX1 - Rx second dubble buffer Data Interrupt 106 4 - RXXFR - Rx Transfer Interrupt 107 5 - EVENT_A - Event Mailbox interrupt [all …]
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