Lines Matching +full:rx +full:- +full:max +full:- +full:burst
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include <linux/dma-mapping.h>
30 #include <linux/dma/imx-dma.h>
115 void (*rx)(struct spi_imx_data *spi_imx); member
138 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
143 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
148 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
153 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
159 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
161 if (spi_imx->rx_buf) { \
162 *(type *)spi_imx->rx_buf = val; \
163 spi_imx->rx_buf += sizeof(type); \
166 spi_imx->remainder -= sizeof(type); \
174 if (spi_imx->tx_buf) { \
175 val = *(type *)spi_imx->tx_buf; \
176 spi_imx->tx_buf += sizeof(type); \
179 spi_imx->count -= sizeof(type); \
181 writel(val, spi_imx->base + MXC_CSPITXDATA); \
199 unsigned int fspi, unsigned int max, unsigned int *fres) in spi_imx_clkdiv_1() argument
203 for (i = 2; i < max; i++) in spi_imx_clkdiv_1()
243 if (!use_dma || controller->fallback) in spi_imx_can_dma()
246 if (!controller->dma_rx) in spi_imx_can_dma()
249 if (spi_imx->target_mode) in spi_imx_can_dma()
252 if (transfer->len < spi_imx->devtype_data->fifo_size) in spi_imx_can_dma()
255 spi_imx->dynamic_burst = 0; in spi_imx_can_dma()
264 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
312 * As measured on the i.MX6, the SPI host controller inserts a 4 SPI-Clock
313 * (SCLK) delay after each burst if the PERIOD reg is 0x0. This value will be
317 * MX51_ECSPI_PERIOD_MIN_DELAY_SCK + register value + 1 SCLK after each burst.
326 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
328 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap_u32()
332 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_rx_swap_u32()
338 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
339 spi_imx->rx_buf += sizeof(u32); in spi_imx_buf_rx_swap_u32()
342 spi_imx->remainder -= sizeof(u32); in spi_imx_buf_rx_swap_u32()
350 unaligned = spi_imx->remainder % 4; in spi_imx_buf_rx_swap()
357 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_rx_swap()
362 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
364 while (unaligned--) { in spi_imx_buf_rx_swap()
365 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap()
366 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; in spi_imx_buf_rx_swap()
367 spi_imx->rx_buf++; in spi_imx_buf_rx_swap()
369 spi_imx->remainder--; in spi_imx_buf_rx_swap()
380 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap_u32()
381 val = *(u32 *)spi_imx->tx_buf; in spi_imx_buf_tx_swap_u32()
382 spi_imx->tx_buf += sizeof(u32); in spi_imx_buf_tx_swap_u32()
385 spi_imx->count -= sizeof(u32); in spi_imx_buf_tx_swap_u32()
387 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_tx_swap_u32()
394 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
402 unaligned = spi_imx->count % 4; in spi_imx_buf_tx_swap()
409 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_tx_swap()
414 while (unaligned--) { in spi_imx_buf_tx_swap()
415 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap()
416 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); in spi_imx_buf_tx_swap()
417 spi_imx->tx_buf++; in spi_imx_buf_tx_swap()
419 spi_imx->count--; in spi_imx_buf_tx_swap()
422 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
427 u32 val = ioread32be(spi_imx->base + MXC_CSPIRXDATA); in mx53_ecspi_rx_target()
429 if (spi_imx->rx_buf) { in mx53_ecspi_rx_target()
430 int n_bytes = spi_imx->target_burst % sizeof(val); in mx53_ecspi_rx_target()
435 memcpy(spi_imx->rx_buf, in mx53_ecspi_rx_target()
436 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); in mx53_ecspi_rx_target()
438 spi_imx->rx_buf += n_bytes; in mx53_ecspi_rx_target()
439 spi_imx->target_burst -= n_bytes; in mx53_ecspi_rx_target()
442 spi_imx->remainder -= sizeof(u32); in mx53_ecspi_rx_target()
448 int n_bytes = spi_imx->count % sizeof(val); in mx53_ecspi_tx_target()
453 if (spi_imx->tx_buf) { in mx53_ecspi_tx_target()
454 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, in mx53_ecspi_tx_target()
455 spi_imx->tx_buf, n_bytes); in mx53_ecspi_tx_target()
456 spi_imx->tx_buf += n_bytes; in mx53_ecspi_tx_target()
459 spi_imx->count -= n_bytes; in mx53_ecspi_tx_target()
461 iowrite32be(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_target()
469 * there are two 4-bit dividers, the pre-divider divides by in mx51_ecspi_clkdiv()
470 * $pre, the post-divider by 2^$post in mx51_ecspi_clkdiv()
473 unsigned int fin = spi_imx->spi_clk; in mx51_ecspi_clkdiv()
477 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
483 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
485 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", in mx51_ecspi_clkdiv()
490 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
492 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", in mx51_ecspi_clkdiv()
515 writel(val, spi_imx->base + MX51_ECSPI_INT); in mx51_ecspi_intctrl()
522 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
524 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
531 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
533 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
540 return spi->controller->unused_native_cs; in mx51_ecspi_channel()
546 struct spi_device *spi = msg->spi; in mx51_ecspi_prepare_message()
551 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
556 if (spi_imx->target_mode) in mx51_ecspi_prepare_message()
564 if (spi->mode & SPI_READY) in mx51_ecspi_prepare_message()
565 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); in mx51_ecspi_prepare_message()
574 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_message()
576 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
577 if (spi->mode & SPI_LOOP) in mx51_ecspi_prepare_message()
581 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
584 * eCSPI burst completion by Chip Select signal in Target mode in mx51_ecspi_prepare_message()
585 * is not functional for imx53 Soc, config SPI burst completed when in mx51_ecspi_prepare_message()
588 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_message()
593 if (spi->mode & SPI_CPOL) { in mx51_ecspi_prepare_message()
601 if (spi->mode & SPI_MOSI_IDLE_LOW) in mx51_ecspi_prepare_message()
606 if (spi->mode & SPI_CS_HIGH) in mx51_ecspi_prepare_message()
614 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
627 * Because spi_imx->spi_bus_clk is only set in prepare_message in mx51_ecspi_prepare_message()
633 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in mx51_ecspi_prepare_message()
634 if (!xfer->speed_hz) in mx51_ecspi_prepare_message()
636 min_speed_hz = min(xfer->speed_hz, min_speed_hz); in mx51_ecspi_prepare_message()
651 bool cpha = (spi->mode & SPI_CPHA); in mx51_configure_cpha()
652 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; in mx51_configure_cpha()
653 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
664 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
670 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
676 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_transfer()
677 ctrl |= (spi_imx->target_burst * 8 - 1) in mx51_ecspi_prepare_transfer()
680 ctrl |= (spi_imx->bits_per_word - 1) in mx51_ecspi_prepare_transfer()
687 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); in mx51_ecspi_prepare_transfer()
688 spi_imx->spi_bus_clk = clk; in mx51_ecspi_prepare_transfer()
696 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed) in mx51_ecspi_prepare_transfer()
701 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
704 if (t->word_delay.value == 0) { in mx51_ecspi_prepare_transfer()
706 } else if (t->word_delay.unit == SPI_DELAY_UNIT_SCK) { in mx51_ecspi_prepare_transfer()
707 word_delay_sck = t->word_delay.value; in mx51_ecspi_prepare_transfer()
714 word_delay_sck -= MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1; in mx51_ecspi_prepare_transfer()
718 word_delay_ns = spi_delay_to_ns(&t->word_delay, t); in mx51_ecspi_prepare_transfer()
724 spi_imx->spi_bus_clk)) { in mx51_ecspi_prepare_transfer()
728 spi_imx->spi_bus_clk)) { in mx51_ecspi_prepare_transfer()
731 word_delay_ns -= mul_u64_u32_div(NSEC_PER_SEC, in mx51_ecspi_prepare_transfer()
733 spi_imx->spi_bus_clk); in mx51_ecspi_prepare_transfer()
735 word_delay_sck = DIV_U64_ROUND_UP((u64)word_delay_ns * spi_imx->spi_bus_clk, in mx51_ecspi_prepare_transfer()
741 return -EINVAL; in mx51_ecspi_prepare_transfer()
744 spi_imx->base + MX51_ECSPI_PERIOD); in mx51_ecspi_prepare_transfer()
753 if (spi_imx->devtype_data->tx_glitch_fixed) in mx51_setup_wml()
754 tx_wml = spi_imx->wml; in mx51_setup_wml()
759 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | in mx51_setup_wml()
761 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | in mx51_setup_wml()
763 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); in mx51_setup_wml()
768 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; in mx51_ecspi_rx_available()
775 readl(spi_imx->base + MXC_CSPIRXDATA); in mx51_ecspi_reset()
818 writel(val, spi_imx->base + MXC_CSPIINT); in mx31_intctrl()
825 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
827 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
842 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx31_prepare_transfer()
844 spi_imx->spi_bus_clk = clk; in mx31_prepare_transfer()
847 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; in mx31_prepare_transfer()
850 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; in mx31_prepare_transfer()
853 if (spi->mode & SPI_CPHA) in mx31_prepare_transfer()
855 if (spi->mode & SPI_CPOL) in mx31_prepare_transfer()
857 if (spi->mode & SPI_CS_HIGH) in mx31_prepare_transfer()
864 if (spi_imx->usedma) in mx31_prepare_transfer()
867 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_prepare_transfer()
869 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
870 if (spi->mode & SPI_LOOP) in mx31_prepare_transfer()
874 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
876 if (spi_imx->usedma) { in mx31_prepare_transfer()
882 spi_imx->base + MX31_CSPI_DMAREG); in mx31_prepare_transfer()
890 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; in mx31_rx_available()
896 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) in mx31_reset()
897 readl(spi_imx->base + MXC_CSPIRXDATA); in mx31_reset()
922 writel(val, spi_imx->base + MXC_CSPIINT); in mx21_intctrl()
929 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
931 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
944 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; in mx21_prepare_transfer() local
947 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) in mx21_prepare_transfer()
949 spi_imx->spi_bus_clk = clk; in mx21_prepare_transfer()
951 reg |= spi_imx->bits_per_word - 1; in mx21_prepare_transfer()
953 if (spi->mode & SPI_CPHA) in mx21_prepare_transfer()
955 if (spi->mode & SPI_CPOL) in mx21_prepare_transfer()
957 if (spi->mode & SPI_CS_HIGH) in mx21_prepare_transfer()
962 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_prepare_transfer()
969 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; in mx21_rx_available()
974 writel(1, spi_imx->base + MXC_RESET); in mx21_reset()
997 writel(val, spi_imx->base + MXC_CSPIINT); in mx1_intctrl()
1004 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
1006 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
1021 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx1_prepare_transfer()
1023 spi_imx->spi_bus_clk = clk; in mx1_prepare_transfer()
1025 reg |= spi_imx->bits_per_word - 1; in mx1_prepare_transfer()
1027 if (spi->mode & SPI_CPHA) in mx1_prepare_transfer()
1029 if (spi->mode & SPI_CPOL) in mx1_prepare_transfer()
1032 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_prepare_transfer()
1039 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; in mx1_rx_available()
1044 writel(1, spi_imx->base + MXC_RESET); in mx1_reset()
1167 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1168 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1169 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1170 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1171 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1172 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1173 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1174 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1183 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1185 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); in spi_imx_set_burst_len()
1186 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1195 * current burst is 0. This only applies when bits_per_word is a in spi_imx_push()
1198 if (!spi_imx->remainder) { in spi_imx_push()
1199 if (spi_imx->dynamic_burst) { in spi_imx_push()
1202 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; in spi_imx_push()
1209 spi_imx->remainder = burst_len; in spi_imx_push()
1211 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_push()
1215 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { in spi_imx_push()
1216 if (!spi_imx->count) in spi_imx_push()
1218 if (spi_imx->dynamic_burst && in spi_imx_push()
1219 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) in spi_imx_push()
1221 spi_imx->tx(spi_imx); in spi_imx_push()
1222 spi_imx->txfifo++; in spi_imx_push()
1225 if (!spi_imx->target_mode) in spi_imx_push()
1226 spi_imx->devtype_data->trigger(spi_imx); in spi_imx_push()
1233 while (spi_imx->txfifo && in spi_imx_isr()
1234 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_isr()
1235 spi_imx->rx(spi_imx); in spi_imx_isr()
1236 spi_imx->txfifo--; in spi_imx_isr()
1239 if (spi_imx->count) { in spi_imx_isr()
1244 if (spi_imx->txfifo) { in spi_imx_isr()
1245 /* No data left to push, but still waiting for rx data, in spi_imx_isr()
1248 spi_imx->devtype_data->intctrl( in spi_imx_isr()
1253 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_isr()
1254 complete(&spi_imx->xfer_done); in spi_imx_isr()
1263 struct dma_slave_config rx = {}, tx = {}; in spi_imx_dma_configure() local
1266 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { in spi_imx_dma_configure()
1277 return -EINVAL; in spi_imx_dma_configure()
1281 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; in spi_imx_dma_configure()
1283 tx.dst_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1284 ret = dmaengine_slave_config(controller->dma_tx, &tx); in spi_imx_dma_configure()
1286 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1290 rx.direction = DMA_DEV_TO_MEM; in spi_imx_dma_configure()
1291 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; in spi_imx_dma_configure()
1292 rx.src_addr_width = buswidth; in spi_imx_dma_configure()
1293 rx.src_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1294 ret = dmaengine_slave_config(controller->dma_rx, &rx); in spi_imx_dma_configure()
1296 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1306 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_setupxfer()
1311 if (!t->speed_hz) { in spi_imx_setupxfer()
1312 if (!spi->max_speed_hz) { in spi_imx_setupxfer()
1313 dev_err(&spi->dev, "no speed_hz provided!\n"); in spi_imx_setupxfer()
1314 return -EINVAL; in spi_imx_setupxfer()
1316 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); in spi_imx_setupxfer()
1317 spi_imx->spi_bus_clk = spi->max_speed_hz; in spi_imx_setupxfer()
1319 spi_imx->spi_bus_clk = t->speed_hz; in spi_imx_setupxfer()
1321 spi_imx->bits_per_word = t->bits_per_word; in spi_imx_setupxfer()
1322 spi_imx->count = t->len; in spi_imx_setupxfer()
1325 * Initialize the functions for transfer. To transfer non byte-aligned in spi_imx_setupxfer()
1326 * words, we have to use multiple word-size bursts. To insert word in spi_imx_setupxfer()
1327 * delay, the burst size has to equal the word size. We can't use in spi_imx_setupxfer()
1330 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode && in spi_imx_setupxfer()
1331 !(spi->mode & SPI_CS_WORD) && in spi_imx_setupxfer()
1332 !(t->word_delay.value) && in spi_imx_setupxfer()
1333 (spi_imx->bits_per_word == 8 || in spi_imx_setupxfer()
1334 spi_imx->bits_per_word == 16 || in spi_imx_setupxfer()
1335 spi_imx->bits_per_word == 32)) { in spi_imx_setupxfer()
1337 spi_imx->rx = spi_imx_buf_rx_swap; in spi_imx_setupxfer()
1338 spi_imx->tx = spi_imx_buf_tx_swap; in spi_imx_setupxfer()
1339 spi_imx->dynamic_burst = 1; in spi_imx_setupxfer()
1342 if (spi_imx->bits_per_word <= 8) { in spi_imx_setupxfer()
1343 spi_imx->rx = spi_imx_buf_rx_u8; in spi_imx_setupxfer()
1344 spi_imx->tx = spi_imx_buf_tx_u8; in spi_imx_setupxfer()
1345 } else if (spi_imx->bits_per_word <= 16) { in spi_imx_setupxfer()
1346 spi_imx->rx = spi_imx_buf_rx_u16; in spi_imx_setupxfer()
1347 spi_imx->tx = spi_imx_buf_tx_u16; in spi_imx_setupxfer()
1349 spi_imx->rx = spi_imx_buf_rx_u32; in spi_imx_setupxfer()
1350 spi_imx->tx = spi_imx_buf_tx_u32; in spi_imx_setupxfer()
1352 spi_imx->dynamic_burst = 0; in spi_imx_setupxfer()
1355 if (spi_imx_can_dma(spi_imx->controller, spi, t)) in spi_imx_setupxfer()
1356 spi_imx->usedma = true; in spi_imx_setupxfer()
1358 spi_imx->usedma = false; in spi_imx_setupxfer()
1360 spi_imx->rx_only = ((t->tx_buf == NULL) in spi_imx_setupxfer()
1361 || (t->tx_buf == spi->controller->dummy_tx)); in spi_imx_setupxfer()
1363 if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) { in spi_imx_setupxfer()
1364 spi_imx->rx = mx53_ecspi_rx_target; in spi_imx_setupxfer()
1365 spi_imx->tx = mx53_ecspi_tx_target; in spi_imx_setupxfer()
1366 spi_imx->target_burst = t->len; in spi_imx_setupxfer()
1369 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t); in spi_imx_setupxfer()
1376 struct spi_controller *controller = spi_imx->controller; in spi_imx_sdma_exit()
1378 if (controller->dma_rx) { in spi_imx_sdma_exit()
1379 dma_release_channel(controller->dma_rx); in spi_imx_sdma_exit()
1380 controller->dma_rx = NULL; in spi_imx_sdma_exit()
1383 if (controller->dma_tx) { in spi_imx_sdma_exit()
1384 dma_release_channel(controller->dma_tx); in spi_imx_sdma_exit()
1385 controller->dma_tx = NULL; in spi_imx_sdma_exit()
1394 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; in spi_imx_sdma_init()
1397 controller->dma_tx = dma_request_chan(dev, "tx"); in spi_imx_sdma_init()
1398 if (IS_ERR(controller->dma_tx)) { in spi_imx_sdma_init()
1399 ret = PTR_ERR(controller->dma_tx); in spi_imx_sdma_init()
1401 controller->dma_tx = NULL; in spi_imx_sdma_init()
1405 /* Prepare for RX : */ in spi_imx_sdma_init()
1406 controller->dma_rx = dma_request_chan(dev, "rx"); in spi_imx_sdma_init()
1407 if (IS_ERR(controller->dma_rx)) { in spi_imx_sdma_init()
1408 ret = PTR_ERR(controller->dma_rx); in spi_imx_sdma_init()
1409 dev_err_probe(dev, ret, "can't get the RX DMA channel!\n"); in spi_imx_sdma_init()
1410 controller->dma_rx = NULL; in spi_imx_sdma_init()
1414 init_completion(&spi_imx->dma_rx_completion); in spi_imx_sdma_init()
1415 init_completion(&spi_imx->dma_tx_completion); in spi_imx_sdma_init()
1416 controller->can_dma = spi_imx_can_dma; in spi_imx_sdma_init()
1417 controller->max_dma_len = MAX_SDMA_BD_BYTES; in spi_imx_sdma_init()
1418 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX | in spi_imx_sdma_init()
1431 complete(&spi_imx->dma_rx_completion); in spi_imx_dma_rx_callback()
1438 complete(&spi_imx->dma_tx_completion); in spi_imx_dma_tx_callback()
1446 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; in spi_imx_calculate_timeout()
1461 struct spi_controller *controller = spi_imx->controller; in spi_imx_dma_transfer()
1462 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in spi_imx_dma_transfer() local
1463 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); in spi_imx_dma_transfer()
1467 /* Get the right burst length from the last sg to ensure no tail data */ in spi_imx_dma_transfer()
1468 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); in spi_imx_dma_transfer()
1469 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { in spi_imx_dma_transfer()
1473 /* Use 1 as wml in case no available burst length got */ in spi_imx_dma_transfer()
1477 spi_imx->wml = i; in spi_imx_dma_transfer()
1483 if (!spi_imx->devtype_data->setup_wml) { in spi_imx_dma_transfer()
1484 dev_err(spi_imx->dev, "No setup_wml()?\n"); in spi_imx_dma_transfer()
1485 ret = -EINVAL; in spi_imx_dma_transfer()
1488 spi_imx->devtype_data->setup_wml(spi_imx); in spi_imx_dma_transfer()
1491 * The TX DMA setup starts the transfer, so make sure RX is configured in spi_imx_dma_transfer()
1494 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in spi_imx_dma_transfer()
1495 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in spi_imx_dma_transfer()
1498 ret = -EINVAL; in spi_imx_dma_transfer()
1502 desc_rx->callback = spi_imx_dma_rx_callback; in spi_imx_dma_transfer()
1503 desc_rx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1505 reinit_completion(&spi_imx->dma_rx_completion); in spi_imx_dma_transfer()
1506 dma_async_issue_pending(controller->dma_rx); in spi_imx_dma_transfer()
1508 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in spi_imx_dma_transfer()
1509 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in spi_imx_dma_transfer()
1512 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1513 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1514 return -EINVAL; in spi_imx_dma_transfer()
1517 desc_tx->callback = spi_imx_dma_tx_callback; in spi_imx_dma_transfer()
1518 desc_tx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1520 reinit_completion(&spi_imx->dma_tx_completion); in spi_imx_dma_transfer()
1521 dma_async_issue_pending(controller->dma_tx); in spi_imx_dma_transfer()
1523 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_dma_transfer()
1526 time_left = wait_for_completion_timeout(&spi_imx->dma_tx_completion, in spi_imx_dma_transfer()
1529 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); in spi_imx_dma_transfer()
1530 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1531 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1532 return -ETIMEDOUT; in spi_imx_dma_transfer()
1535 time_left = wait_for_completion_timeout(&spi_imx->dma_rx_completion, in spi_imx_dma_transfer()
1538 dev_err(&controller->dev, "I/O Error in DMA RX\n"); in spi_imx_dma_transfer()
1539 spi_imx->devtype_data->reset(spi_imx); in spi_imx_dma_transfer()
1540 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1541 return -ETIMEDOUT; in spi_imx_dma_transfer()
1547 transfer->error |= SPI_TRANS_FAIL_NO_START; in spi_imx_dma_transfer()
1554 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer()
1558 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer()
1559 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer()
1560 spi_imx->count = transfer->len; in spi_imx_pio_transfer()
1561 spi_imx->txfifo = 0; in spi_imx_pio_transfer()
1562 spi_imx->remainder = 0; in spi_imx_pio_transfer()
1564 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer()
1568 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); in spi_imx_pio_transfer()
1570 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_pio_transfer()
1572 time_left = wait_for_completion_timeout(&spi_imx->xfer_done, in spi_imx_pio_transfer()
1575 dev_err(&spi->dev, "I/O Error in PIO\n"); in spi_imx_pio_transfer()
1576 spi_imx->devtype_data->reset(spi_imx); in spi_imx_pio_transfer()
1577 return -ETIMEDOUT; in spi_imx_pio_transfer()
1586 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_poll_transfer()
1589 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_poll_transfer()
1590 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_poll_transfer()
1591 spi_imx->count = transfer->len; in spi_imx_poll_transfer()
1592 spi_imx->txfifo = 0; in spi_imx_poll_transfer()
1593 spi_imx->remainder = 0; in spi_imx_poll_transfer()
1601 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies; in spi_imx_poll_transfer()
1602 while (spi_imx->txfifo) { in spi_imx_poll_transfer()
1603 /* RX */ in spi_imx_poll_transfer()
1604 while (spi_imx->txfifo && in spi_imx_poll_transfer()
1605 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_poll_transfer()
1606 spi_imx->rx(spi_imx); in spi_imx_poll_transfer()
1607 spi_imx->txfifo--; in spi_imx_poll_transfer()
1611 if (spi_imx->count) { in spi_imx_poll_transfer()
1616 if (spi_imx->txfifo && in spi_imx_poll_transfer()
1619 dev_err_ratelimited(&spi->dev, in spi_imx_poll_transfer()
1620 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n", in spi_imx_poll_transfer()
1621 jiffies - timeout); in spi_imx_poll_transfer()
1634 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer_target()
1638 transfer->len > MX53_MAX_TRANSFER_BYTES) { in spi_imx_pio_transfer_target()
1639 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", in spi_imx_pio_transfer_target()
1641 return -EMSGSIZE; in spi_imx_pio_transfer_target()
1644 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer_target()
1645 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer_target()
1646 spi_imx->count = transfer->len; in spi_imx_pio_transfer_target()
1647 spi_imx->txfifo = 0; in spi_imx_pio_transfer_target()
1648 spi_imx->remainder = 0; in spi_imx_pio_transfer_target()
1650 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer_target()
1651 spi_imx->target_aborted = false; in spi_imx_pio_transfer_target()
1655 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); in spi_imx_pio_transfer_target()
1657 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || in spi_imx_pio_transfer_target()
1658 spi_imx->target_aborted) { in spi_imx_pio_transfer_target()
1659 dev_dbg(&spi->dev, "interrupted\n"); in spi_imx_pio_transfer_target()
1660 ret = -EINTR; in spi_imx_pio_transfer_target()
1669 if (spi_imx->devtype_data->disable) in spi_imx_pio_transfer_target()
1670 spi_imx->devtype_data->disable(spi_imx); in spi_imx_pio_transfer_target()
1679 result = DIV_U64_ROUND_CLOSEST((u64)USEC_PER_SEC * transfer->len * BITS_PER_BYTE, in spi_imx_transfer_estimate_time_us()
1680 transfer->effective_speed_hz); in spi_imx_transfer_estimate_time_us()
1681 if (transfer->word_delay.value) { in spi_imx_transfer_estimate_time_us()
1685 words = DIV_ROUND_UP(transfer->len * BITS_PER_BYTE, transfer->bits_per_word); in spi_imx_transfer_estimate_time_us()
1686 word_delay_us = DIV_ROUND_CLOSEST(spi_delay_to_ns(&transfer->word_delay, transfer), in spi_imx_transfer_estimate_time_us()
1698 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_transfer_one()
1701 transfer->effective_speed_hz = spi_imx->spi_bus_clk; in spi_imx_transfer_one()
1704 while (spi_imx->devtype_data->rx_available(spi_imx)) in spi_imx_transfer_one()
1705 readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_transfer_one()
1707 if (spi_imx->target_mode) in spi_imx_transfer_one()
1715 if (spi_imx->usedma) in spi_imx_transfer_one()
1719 if (transfer->len == 1 || (polling_limit_us && in spi_imx_transfer_one()
1728 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, in spi_imx_setup()
1729 spi->mode, spi->bits_per_word, spi->max_speed_hz); in spi_imx_setup()
1740 ret = pm_runtime_resume_and_get(spi_imx->dev); in spi_imx_prepare_message()
1742 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_prepare_message()
1746 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); in spi_imx_prepare_message()
1748 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_prepare_message()
1749 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_prepare_message()
1760 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_unprepare_message()
1761 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_unprepare_message()
1769 spi_imx->target_aborted = true; in spi_imx_target_abort()
1770 complete(&spi_imx->xfer_done); in spi_imx_target_abort()
1777 struct device_node *np = pdev->dev.of_node; in spi_imx_probe()
1783 of_device_get_match_data(&pdev->dev); in spi_imx_probe()
1787 target_mode = devtype_data->has_targetmode && in spi_imx_probe()
1788 of_property_read_bool(np, "spi-slave"); in spi_imx_probe()
1790 controller = spi_alloc_target(&pdev->dev, in spi_imx_probe()
1793 controller = spi_alloc_host(&pdev->dev, in spi_imx_probe()
1796 return -ENOMEM; in spi_imx_probe()
1798 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); in spi_imx_probe()
1806 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in spi_imx_probe()
1807 controller->bus_num = np ? -1 : pdev->id; in spi_imx_probe()
1808 controller->use_gpio_descriptors = true; in spi_imx_probe()
1811 spi_imx->controller = controller; in spi_imx_probe()
1812 spi_imx->dev = &pdev->dev; in spi_imx_probe()
1813 spi_imx->target_mode = target_mode; in spi_imx_probe()
1815 spi_imx->devtype_data = devtype_data; in spi_imx_probe()
1823 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) in spi_imx_probe()
1824 controller->num_chipselect = val; in spi_imx_probe()
1826 controller->num_chipselect = 3; in spi_imx_probe()
1828 controller->transfer_one = spi_imx_transfer_one; in spi_imx_probe()
1829 controller->setup = spi_imx_setup; in spi_imx_probe()
1830 controller->prepare_message = spi_imx_prepare_message; in spi_imx_probe()
1831 controller->unprepare_message = spi_imx_unprepare_message; in spi_imx_probe()
1832 controller->target_abort = spi_imx_target_abort; in spi_imx_probe()
1833 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS | in spi_imx_probe()
1838 controller->mode_bits |= SPI_LOOP | SPI_READY; in spi_imx_probe()
1841 controller->mode_bits |= SPI_RX_CPHA_FLIP; in spi_imx_probe()
1844 device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) in spi_imx_probe()
1846 * When using HW-CS implementing SPI_CS_WORD can be done by just in spi_imx_probe()
1847 * setting the burst length to the word size. This is in spi_imx_probe()
1850 controller->mode_bits |= SPI_CS_WORD; in spi_imx_probe()
1853 controller->max_native_cs = 4; in spi_imx_probe()
1854 controller->flags |= SPI_CONTROLLER_GPIO_SS; in spi_imx_probe()
1857 spi_imx->spi_drctl = spi_drctl; in spi_imx_probe()
1859 init_completion(&spi_imx->xfer_done); in spi_imx_probe()
1861 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in spi_imx_probe()
1862 if (IS_ERR(spi_imx->base)) { in spi_imx_probe()
1863 ret = PTR_ERR(spi_imx->base); in spi_imx_probe()
1866 spi_imx->base_phys = res->start; in spi_imx_probe()
1874 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, in spi_imx_probe()
1875 dev_name(&pdev->dev), spi_imx); in spi_imx_probe()
1877 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in spi_imx_probe()
1881 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in spi_imx_probe()
1882 if (IS_ERR(spi_imx->clk_ipg)) { in spi_imx_probe()
1883 ret = PTR_ERR(spi_imx->clk_ipg); in spi_imx_probe()
1887 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); in spi_imx_probe()
1888 if (IS_ERR(spi_imx->clk_per)) { in spi_imx_probe()
1889 ret = PTR_ERR(spi_imx->clk_per); in spi_imx_probe()
1893 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_probe()
1897 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_probe()
1901 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); in spi_imx_probe()
1902 pm_runtime_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1903 pm_runtime_get_noresume(spi_imx->dev); in spi_imx_probe()
1904 pm_runtime_set_active(spi_imx->dev); in spi_imx_probe()
1905 pm_runtime_enable(spi_imx->dev); in spi_imx_probe()
1907 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); in spi_imx_probe()
1912 if (spi_imx->devtype_data->has_dmamode) { in spi_imx_probe()
1913 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller); in spi_imx_probe()
1914 if (ret == -EPROBE_DEFER) in spi_imx_probe()
1918 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", in spi_imx_probe()
1922 spi_imx->devtype_data->reset(spi_imx); in spi_imx_probe()
1924 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_probe()
1926 controller->dev.of_node = pdev->dev.of_node; in spi_imx_probe()
1929 dev_err_probe(&pdev->dev, ret, "register controller failed\n"); in spi_imx_probe()
1933 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_probe()
1934 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_probe()
1939 if (spi_imx->devtype_data->has_dmamode) in spi_imx_probe()
1942 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1943 pm_runtime_disable(spi_imx->dev); in spi_imx_probe()
1944 pm_runtime_set_suspended(&pdev->dev); in spi_imx_probe()
1946 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_probe()
1948 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_probe()
1963 ret = pm_runtime_get_sync(spi_imx->dev); in spi_imx_remove()
1965 writel(0, spi_imx->base + MXC_CSPICTRL); in spi_imx_remove()
1967 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n"); in spi_imx_remove()
1969 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_remove()
1970 pm_runtime_put_sync(spi_imx->dev); in spi_imx_remove()
1971 pm_runtime_disable(spi_imx->dev); in spi_imx_remove()
1984 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_runtime_resume()
1988 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_runtime_resume()
1990 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_resume()
2004 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_suspend()
2005 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_runtime_suspend()